PRELIMINARY
INTEL 430MX PCISET
82437MX MOBILE SYSTEM CONTROLLER (MTSC)
AND 82438MX MOBILE DATA PATH (MTDP)
Supports the Pentium
®
Processor at
iCOMP
®
Index 815\100 MHz, iCOMP
Index 735/90 MHz, iCOMP Index
1000/120, and the 75 MHz Pentium
Processor
Integrated Second Level Cache
Controller
Direct Mapped Organization
Write-Back Cache Policy
Cacheless, 256 Kbytes, and
512 Kbytes
Standard, Burst and Pipelined Burst
SRAMs
Cache Hit Read/Write Cycle Timings
at 3-1-1-1 with Burst or Pipelined
Burst SRAMs
Back-to-Back Read Cycles at
3-1-1-1-1-1-1-1 with Burst or
Pipelined Burst SRAMs
Integrated Tag/Valid Status Bits for
Cost Savings and Performance
Supports 3.3V SRAMs for Tag
Address
Integrated DRAM Controller
64-Bit Data Path to Memory
4 Mbytes to 128 Mbytes Main
Memory
EDO/Hyper Page Mode DRAM
(x-2-2-2 Reads) Provides Superior
Cacheless Designs
Standard Page Mode DRAMs
4 RAS Lines
4-Qword Deep Buffer for 3-1-1-1
Posted Write Cycles
Symmetrical and Asymmetrical
DRAMs
3V or 5V DRAMs
Fully Synchronous 25/30/33 MHz PCI
Bus Interface
100 MB/s Instant Access Enables
Native Signal Processing on Pentium
Processors
Synchronized CPU-to-PCI Interface
for High Performance Graphics
PCI Bus Arbiter: MPIIX and Three PCI
Bus Masters Supported
CPU-to-PCI Memory Write Posting
with 4-Dword Deep Buffers
Converts Back-to-Back Sequential
CPU to PCI Memory Writes to PCI
Burst Writes
PCI-to-DRAM Posting of 12 Dwords
PCI-to-DRAM up to 120 MB/s
Bandwidth Utilizing Snoop Ahead
Feature
NAND Tree for Board-Level ATE Testing
208-Pin QFP for the 82437MX System
Controller (MTSC); 100-Pin TQFP for
Each 82438MX Data Path (MTDP)
The Intel 430MX PCIset consists of the 82437MX System Controller (MTSC), two 82438MX Data Paths
(MTDP), and the 82371MX PCI I/O IDE Xcelerator (MPIIX). The PCIset forms a Host-to-PCI bridge and provides
the second level cache control and a full function 64-bit data path to main memory. The MTSC integrates the
cache and main memory DRAM control functions and provides bus control for transfers between the CPU,
cache, main memory, and the PCI Bus. The second level (L2) cache controller supports a write-back cache
policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache
memory can be implemented with either standard, burst, or pipelined burst SRAMs. An external Tag RAM is
used for the address tag and an internal Tag RAM for the cache line status bits. For the MTSC DRAM controller,
four rows are supported for up to 128 Mbytes of main memory. The MTSC optimized PCI interface allows the
CPU to sustain the highest possible bandwidth to the graphics frame buffer at all frequencies. Using the snoop
ahead feature, the MTSC allows PCI masters to achieve full PCI bandwidth. The MTDPs provide the data paths
between the CPU/cache, main memory, and PCI. For increased system performance, the MTDPs contain read
prefetch and posted write buffers.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright,
for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to those
specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1996
April 1996
Order Number: 290524-001
82437MX MTSC AND 82438MX MTDP
A[31:3]
BE[7:0]#
ADS#
D/C#
M/IO#
W/R#
BRDY#
EADS#
HITM#
BOFF#
AHOLD
NA#
KEN#/INV
CACHE#
HLOCK#
SMIACT#
Host
Interface
PCI
Interface
AD[31:0]
C/BE[3:0]#
FRAME#
TRDY#
IRDY#
STOP#
LOCK#
DEVSEL#
PAR
R EQ[2:0]#
G N T[2:0 ]#
PHLD#
PHLDA#
RST#
CLK RU N #
R A S [3 :0 ]#
CC S#
TWE#
COE#
CWE[7:0]#
C A D S # /C A 3 #
C A D V # /C A 4
TIO[7:0]
HCLKIN
PCLKIN
RTC CLK
P W R SD
P W RO K
MTDP
Interface
Clocks
Cache
Interface
DRAM
Interface
CAS[7:0]#
M A [1 1 :0 ]
W E#
PLINK[15:0]
MSTB#
MADV#
PCMD[1:0]
HOE#
MOE#
POE#
Pow er
M gnt.
MTSC_BLK
82437MX MTSC Block Diagram
PLINK[7:0]
D[31:0]
Host
Interface
M T SC
In terface
MSTB#
MADV#
PCMD[1:0]
HOE#
M D [31:0 ]
DRAM
Interface
MOE#
POE#
C lo cks
HCLK
MTDP_BLK
82438MX MTDP Block Diagram
2
PRELIMINARY
82437MX MTSC AND 82438MX MTDP
CONTENTS
1.0. ARCHITECTURE OVERVIEW OF THE INTEL 430MX PCISET
................................ ............................5
.
2.0 SIGNAL DESCRIPTION
................................ ............................... ............................... ..............................7
.
.
.
2.1. MTSC Signals........................................................................................................................................... 7
2.1.1. HOST INTERFACE (MTSC) ............................................................................................................. 7
2.1.2. DRAM INTERFACE (MTSC) ............................................................................................................ 9
2.1.3. SECONDARY CACHE INTERFACE (MTSC) ................................................................................ 9
2.1.4. PCI INTERFACE (MTSC) ............................................................................................................... 10
2.1.5. MTPD INTERFACE (MTSC) ..........................................................................................................12
2.1.6. CLOCKS (MTSC) ............................................................................................................................ 12
2.1.7. POWER MANAGEMENT (MTSC) .................................................................................................13
2.2. MTDP Signals.........................................................................................................................................13
2.2.1. DATA INTERFACE SIGNALS (MTDP) ......................................................................................... 13
2.2.2. MTSC INTERFACE SIGNALS (MTDP) ......................................................................................... 13
2.2.3. CLOCK SIGNAL (MTDP) ................................................................................................................ 14
2.3. Strapping Options ...................................................................................................................................14
3.0. REGISTER DESCRIPTION
................................ ............................... ............................... ......................15
.
.
.
3.1. Control Registers ....................................................................................................................................15
3.1.1. CONFADD—CONFIGURATION ADDRESS REGISTER ............................................................ 15
3.1.2. CONFDATA—CONFIGURATION DATA REGISTER ..................................................................16
3.2. PCI Configuration Registers .................................................................................................................. 16
3.2.1. VIDVENDOR IDENTIFICATION REGISTER ............................................................................ 18
3.2.2. DIDDEVICE IDENTIFICATION REGISTER .............................................................................. 18
3.2.3. PCICMDPCI COMMAND REGISTER ........................................................................................ 18
3.2.4. PCISTSPCI STATUS REGISTER .............................................................................................. 19
3.2.5. RIDREVISION IDENTIFICATION REGISTER ..........................................................................20
3.2.6. CLASSCCLASS CODE REGISTER .......................................................................................... 20
3.2.7. MLTMASTER LATENCY TIMER REGISTER ........................................................................... 20
3.2.8. BISTBIST REGISTER ................................................................................................................. 21
3.2.9. PCONPCI CONTROL REGISTER ............................................................................................. 21
3.2.10. CCCACHE CONTROL REGISTER ......................................................................................... 22
3.2.11. DRAMCDRAM CONTROL REGISTER ................................................................................... 23
3.2.12. DRAMTDRAM TIMING REGISTER ......................................................................................... 24
3.2.13. PAM—PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) ..................................26
3.2.14. DRB—DRAM ROW BOUNDARY REGISTERS .........................................................................28
3.2.15. DRTDRAM ROW TYPE REGISTER ....................................................................................... 29
3.2.16. SMRAMSYSTEM MANAGEMENT RAM CONTROL REGISTER .........................................29
PRELIMINARY
3
82437MX MTSC AND 82438MX MTDP
4.0. FUNCTIONAL DESCRIPTION
................................ ............................... ............................... .................31
.
.
.
4.1. Host Interface ..........................................................................................................................................31
4.2. PCI Interface............................................................................................................................................31
4.3. Secondary Cache Interface ....................................................................................................................32
4.3.1. CLOCK LATENCIES .......................................................................................................................32
4.3.2. SNOOP CYCLES ............................................................................................................................33
4.3.3. SRAM POWER DOWN (DE-SELECT) MODE SEQUENCE .......................................................34
4.3.4. FLUSHING L2 CACHE ...................................................................................................................34
4.3.5. CACHE ORGANIZATION ...............................................................................................................34
4.4. DRAM Interface.......................................................................................................................................38
4.4.1. DRAM ORGANIZATION .................................................................................................................39
4.4.2. MAIN MEMORY ADDRESS MAP ..................................................................................................39
4.4.3. DRAM ADDRESS TRANSLATION ................................................................................................39
4.4.4. DRAM PAGE MODE .......................................................................................................................41
4.4.5. EDO MODE ......................................................................................................................................42
4.4.6. DRAM PERFORMANCE ................................................................................................................43
4.4.7. DRAM REFRESH ............................................................................................................................45
4.4.8. SUSPEND REFRESH ....................................................................................................................46
4.4.9. SYSTEM MANAGEMENT RAM .....................................................................................................46
4.5. 82438MX Data Path (MTDP) .................................................................................................................46
4.6. PCI Bus Arbitration .................................................................................................................................47
4.6.1. PRIORITY SCHEME AND BUS GRANT .......................................................................................48
4.6.2. CPU POLICIES ................................................................................................................................48
4.7. Clocks and Reset ....................................................................................................................................51
4.7.1. CLOCKS...........................................................................................................................................51
4.7.2. RESET SEQUENCING ...................................................................................................................51
4.8. PCI Clock Control (CLKRUN#) ..............................................................................................................53
5.0. PINOUT AND PACKAGE INFORMATION
................................ ............................... ............................. 4
.
.
5
5.1. MTSC Pin Assignment ...........................................................................................................................54
5.2. MTDP Pin Assignment ...........................................................................................................................58
5.3. MTSC Package Characteristics .............................................................................................................61
5.4. MTDP Package Characteristics .............................................................................................................62
6.0. TESTABILITY................................ ............................... ............................... ............................... ............63
.
.
.
.
6.1. 82437MX MTSC TESTABILITY .............................................................................................................63
6.1.1. TEST MODE OPERATION .............................................................................................................63
6.1.2. TEST ISSUES..................................................................................................................................63
6.1.3. NAND TREE TIMING REQUIREMENTS ......................................................................................65
6.2. 82438MX MTDP TESTABILITY ............................................................................................................68
6.2.1. NAND TREE TEST MODE OPERATION ......................................................................................68
4
PRELIMINARY
82437MX MTSC AND 82438MX MTDP
1.0. ARCHITECTURE OVERVIEW OF THE INTEL 430MX PCISET
The Intel 430MX PCIset (Figure 1) consists of the Mobile System Controller (MTSC), two Mobile Data Path
(MTDP) units, and the 82371MB Mobile PCI I/O IDE Xcelerator (MPIIX). The MTSC and two MTDPs form a
Host-to-PCI bridge. The MPIIX is a multi-function PCI device providing a PCI-to-Expansion I/O (ISA-like) bridge
and a fast IDE interface. The MPIIX also provides power management and has a plug-n-play port.
The two MTDPs provide a 64-bit data path to the host and to main memory and provide a 16-bit data path
(PLINK) between the MTSC and MTDP. PLINK provides the data path for CPU to PCI accesses and for PCI to
main memory accesses. The MTSC and MTDP bus interfaces are designed for 3V and 5V busses. The
MTSC/MTDP connects directly to the Pentium® processor 3V host bus; The MTSC/MTDP connects directly to
5V or 3V main memory DRAMs; and the MTSC connects directly to the 5V PCI bus.
DRAM Interface
The DRAM interface is a 64-bit data path that supports both standard page mode and Extended Data Out (EDO)
memory. With 60 ns EDO DRAMs, a 7-2-2-2 cycle time can be achieved at 66 MHz for reads and 3-1-1-1 for
posted writes. The MTSC supports 4 Mbytes to 128 Mbytes with four RAS lines available and also supports
symmetrical and asymmetrical addressing for 512K, 1-, 2-, and 4-Mbyte deep DRAMs. The MTSC supports
CAS-before-RAS refresh (15.6
µs
and Extended-Refresh to 256
µs)
during normal and Suspend modes. In
addition, Self-Refresh is supported for Suspend modes.
Second Level Cache
The MTSC supports a write-back cache policy providing all necessary snoop functions and inquire cycles. The
second level cache is direct mapped and supports both a 256-Kbyte or 512-Kbyte SRAM configuration using
either burst or standard SRAMs. The burst 256-Kbyte configuration performance is 3-1-1-1 for read/write cycles;
pipelined back-to-back reads can maintain a 3-1-1-1-1-1-1-1 transfer rate.
MTDP
Two MTDPs create a 64-bit CPU and main memory data path. The MTDPs also interface to the MTSCs 16-bit
PLINK inter-chip bus for PCI transactions. The combination of the 64-bit memory path and the 16-bit PLINK bus
make the MTDPs a cost-effective solution, providing optimal CPU-to-main memory performance while
maintaining a small package footprint (100 pins each).
PCI Interface
The PCI interface is 2.0 compliant and supports up to 3 PCI bus masters in addition to the MPIIX bus master
requests. While the MTSC and MTDP together provide the interface between PCI and main memory, only the
MTSC connects to the PCI bus.
PRELIMINARY
5
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