12:1 Single-ended Multiplexer
ICS850S1201I
DATA SHEET
General Description
ICS
HiPerClockS™
Features
•
•
•
•
•
•
•
12:1 single-ended multiplexer
Nominal output impedance: 20Ω (V
DD
= 3.3V)
Maximum output frequency: 250MHz
Propagation delay: 2.7ns (maximum)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
The ICS850S1201I is a low skew12:1 Single-ended
Clock Multiplexer. The ICS850S1201I has 12
selectable single-ended clock inputs and 1 single-
ended clock output. The device operates up to
250MHz and is packaged in a 20 TSSOP package.
Block Diagram
CLK_SEL0
Pulldown
CLK_SEL1
Pulldown
CLK_SEL2
Pulldown
CLK_SEL3
Pulldown
CLK0
Pulldown
CLK1
Pulldown
Pin Assignment
CLK8
CLK9
CLK10
CLK11
V
DD
CLK_SEL0
CLK_SEL1
CLK_SEL2
CLK_SEL3
OE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
CLK0
GND
Q
ICS850S1201I
Q
CLK10
Pulldown
CLK11
Pulldown
20-Lead TSSOP
6.50mm x 4.40mm x 0.925mm
package body
G Package
Top View
OE
Pullup
ICS850S1201BGI REVISION A JANUARY 4, 2010
1
©2010 Integrated Device Technology, Inc.
ICS850S1201I Data Sheet
12:1 SINGLE-ENDED MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6,
7.
8,
9
10
11
12
13
14
15
16
17
18
19
20
Name
CLK8
CLK9
CLK10
CLK11
V
DD
CLK_SEL0,
CLK_SEL1,
CLK_SEL2,
CLK_SEL3
OE
Q
GND
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Input
Input
Input
Input
Power
Type
Pulldown
Pulldown
Pulldown
Pulldown
Description
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Power supply pin.
Input
Pulldown
Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels.
Input
Output
Power
Input
Input
Input
Input
Input
Input
Input
Input
Pullup
Output enable pin for Q output. LVCMOS/LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Power supply ground.
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
V
DD
= 3.465V
V
DD
= 2.625V
Test Conditions
Minimum
Typical
2
10
8
51
51
20
25
Maximum
Units
pF
pF
pF
k
Ω
k
Ω
Ω
Ω
ICS850S1201BGI REVISION A JANUARY 4, 2010
2
©2010 Integrated Device Technology, Inc.
ICS850S1201I Data Sheet
12:1 SINGLE-ENDED MULTIPLEXER
Function Tables
Table 3. Clock Input Function Table
Inputs
CLK_SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLK_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLK_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CLK_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Selected to Q
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
Output goes LOW
Output goes LOW
Output goes LOW
Output goes LOW
ICS850S1201BGI REVISION A JANUARY 4, 2010
3
©2010 Integrated Device Technology, Inc.
ICS850S1201I Data Sheet
12:1 SINGLE-ENDED MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
87.2°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Output Unterminated
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
49
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Output Unterminated
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
41
Units
V
mA
ICS850S1201BGI REVISION A JANUARY 4, 2010
4
©2010 Integrated Device Technology, Inc.
ICS850S1201I Data Sheet
12:1 SINGLE-ENDED MULTIPLEXER
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
CLK[0:11],
CLK_SEL[0:3]
OE
Input
Low Current
CLK[0:11],
CLK_SEL[0:3]
OE
V
OH
V
OL
Output High Voltage; NOTE 1
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.3V ± 5%, I
OH
= -12mA
V
DD
= 2.5V ± 5%, I
OH
= -12mA
Output Low Voltage; NOTE 1
V
DD
= 3.3V ± 5% or 2.5V ± 5%,
I
OL
= 12mA
-10
-150
2.6
1.8
0.5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
10
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
IL
I
IH
I
IL
NOTE 1: Output terminated with 50
Ω
to V
DD
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
tp
LH
tjit
tsk(i)
tsk(pp)
t
R
/ t
F
odc
MUX
ISOLATION
Parameter
Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Input Skew
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle; NOTE 4
MUX Isolation
20% to 80%
f
≤
200MHz
f = 250MHz
155.52MHz
100
46
40
43
155.52MHz, Integration
Range: 12kHz – 20MHz
1.4
0.35
175
600
500
54
60
Test Conditions
Minimum
Typical
Maximum
250
2.7
Units
MHz
ns
ps
ps
ps
ps
%
%
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Input duty cycle must be 50%.
ICS850S1201BGI REVISION A JANUARY 4, 2010
5
©2010 Integrated Device Technology, Inc.
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