PF496-05
SED1681F
OA
SED1681F
OA
/D
/D
OA
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lta
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e V tion
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Wi pera cts
O rodu
P
OA
LCD Driver
80 LCD Segment Driver Outputs
Display Duty from 1/8 to 1/32
Expansion Driver
DESCRIPTION
The SED1681 is a dot-matrix LCD segment driver for small, high-contrast display panels with duty cycles ranging
from 1/8 to 1/32. The segment driver incorporates 80 driver circuits with input and output data interfaced serially.
The SED1681 is designed for use as a display expansion driver for use either with dedicated LCD controllers
such as the SED1278F, or with 4-bit micro-controller devices. It also shares a common interface with the
SED1181F.
The SED1681 is available as die form (SED1681D
0A
) or in 100-pin QFPs (SED1681F
0A
).
FEATURES
80 LCD segment driver output
Display duty ranging from 1/8 to 1/32
Serial input and output data pins
Die (SED1681D
0A
) or QFP5-100pin (SED1681F
0A
)
Package ................................................ QFP5-100pin (plastic): SED1681F
0A
Die form: SED1681D
0A
BLOCK DIAGRAM
V
SS
V
DD
SEG0 1
2
79
V0
V2
V3
V5
Voltage
Controller
LCD driver
80 bits
FR
Level Shifter 80 bits
LP
Latch 80 bits
D1
D0
Data
Controller
Bidirectional Shift Register
SHL
XSCL
1
SED1681F
OA
/D
OA
PIN CONFIGURATION
QFP5-100pin
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
80
81
85
75
70
65
60
55
51
50
45
90
SED1681F
0A
INDEX
40
95
35
100
1
31
5
10
15
20
25
30
NC
NC
NC
NC
V
DD
NC
FR
NC
DO
DI
XSCL
SHL
NC
LP
V
SS
V2
V3
V0
V5
NC
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
*
NC: No Connection
PIN DESCRIPTION
Pin/Pad
Number
Name
1 to 30,
51 to 100
40
40
SEG0 to
SEG79
XSCL
LP
Input/
Output
O
I
I
Function
Liquid crystal segment drive outputs
Segment outputs change on the falling edge of the LP input signal.
Shift clock input
Shift register data is shifted on the falling edge of this signal.
Display data strobe
Data from the shift register is strobed on to the display data latch on the falling edge
of this signal.
Serial data input
Serial data output
Shift direction select
This pin selects the data shift direction from bit 0 towards bit 79 or in reverse.
Liquid crystal frame signal input
Ground
Logic power supply
LCD drive voltage supply inputs
These voltages should satisfy the following conditions.
V
DD
> V0, V
DD
> V
2
>1/2 V
5
, 1/2 > V
5
> V
3
> V
5
=
= =
= = =
No connection
41
42
39
44
46
36
32 to 35
DI
DO
SHL
FR
V
DD
V
SS
V
0
, V
2
,
V
3
, V
5
N.C.
I
O
I
I
—
—
—
31, 38, 43,
45, 47 to 50
—
2
SED1681F
OA
/D
OA
ABSOLUTE MAXIMUM RATINGS
Rating
Supply voltage (1)
Supply voltage (2)
Supply voltage (3)
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Soldering temperature and time (at lead)
Symbol
V
SS
V
5
V
0
, V
2
, V
3
*
V
IN
V
O
P
D
T
OPR
R
STG
T
SOLDER
Value
-7.0 to+0.3
-15.0 to+0.3
-15.0 to+0.3
V
SS
-0.3 to+0.3
V
SS
-0.3 to+0.3
300
-20 to+75
-65 to +150
260˚C, for 10s
(V
DD
=0V)
Unit
V
V
V
V
V
mW
˚C
˚C
—
*1 Never use wave soldering to mount packages, or any other method that applies excessive thermal
stress to a package, as this will reduce its heat dissipation capacity.
ELECTRICAL CHARACTERISTICS
DC Electrical Characteristics
(Unless otherwise specified, V
DD
=V
0
=0V, V
SS
=-5.0V±10%, and Ta=-20 to 75˚C)
Characteristic
Supply voltage (1)
Recommended operating voltage
Permitted operating voltage.
Supply voltage (2)
Supply voltage (3)
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
Quiescent current
Symbol
V
SS
V
5
V
5
V
2
V
3
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
I
Q
I
OH
=-0.6mA
I
OL
=0.6mA
0V < V
IN
< V
SS
=
=
0V < V
OUT
< V
SS
=
=
V
5
=-12.0V
V
SS
=-6.0V, V
IH
=V
CC
V
ON
=0.1V
Ta=25˚C
V
5
=-8.0V
V
5
=-5.0V
V
5
=-3.0V
I
SS
OP
Condition
Pin
V
SS
V
5
V
5
V
2
V
3
D1,
XSCL, LP,
SHL, FR
Min.
-6.0
-12.0
-12.0
1/2
V
5
0.2 V
SS
V
SS
-0.4
—
—
—
—
—
—
—
V
5
Typ.
-5.0
—
—
—
—
—
—
—
—
0.05
0.05
0.05
1.5
3.0
10.0
Max.
-2.4
-3.0
-2.5
V
DD
1/2 V
5
V
DD
0.8 V
SS
—
V
SS
+0.4
2.0
5.0
30.0
3.0
8.0
50.0
Unit
V
V
V
V
V
V
V
V
V
A
A
A
Operational limits
Recommended value
Recommended value
D0
SHL, FR,
XSCL, LP
D0
V
DD
SEG0 to
SEG79
Output resistance
R
SEG
k
Supply current (1)
V
SS
=-5.0V, V
IH
=V
DD
,
V
IL
=V
SS
, f
XSCL
=400KHz
LP=520 s, FR=16.7ms
all data inputs are alternate
1 and 0 data, all output open.
V
SS
=-4.5V, V
2
=-4.8V
V
3
=-7.2V, V
SSH
=-12.0V
other conditions as for l
SSOP
Ta=25˚C
V
SS
—
250
350
A
Supply current (2)
I
5
OP
V
5
SHL, FR,
XSCL, LP
—
10
16
A
Input pin capacitance
C
IN
—
5
8
pF
*1 This parameter specifies the range of V
5
over which operation is possible. The driver ON-resistance for the particular LCD
panel being used may result in V
5
exceeding the recommended operating range. The V
5
operating voltage should be
datermined experimentally and component changes made, if necessary, to ensure operation within the recommended
range.
3
SED1681F
OA
/D
OA
AC Characteristics
Input timing
FR
t
WLPH
t
DFR
LP
t
CLC
t
LT
t
LH
XSCL
t
WCLH
t
WCLL
t
r
t
r
f
DI
t
DS
t
DH
(V
SS
=-6.0V to -2.4V, Ta=-20 to 75˚C)
Characteristic
Shift clock period
Shift clock High-level pulse width
Shift clock Low-level pulse width
Data setup time
Data hold time
Latch pulse High-level pulse width
Shift clock to latch pulse interval
Latch hold time
Frame signal delay time
Input signal rise time
Input signal fall time
Symbol
t
CLC
t
WCLH
t
WCLL
t
DS
t
DH
t
WLPH
t
LT
t
LH
t
DFR
t
r
t
f
Condition
Min.
1.0
450
450
140
100
200
200
100
-500
—
—
Max.
—
—
—
—
—
—
—
—
+500
50
50
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output timing
FR
t
FRSD
LP
XSCL
D0
SEG
t
PD
t
LPSD
(
Characteristic
Serial data oupput delay time
LP to segment output delay time
FR to segment output dalay time
Symbol
t
PD
t
LPSD
t
FRSD
Condition
CL=15pF
CL=100pF
V
SS
=-6.0V to -2.4V
V
5
=-12.0V to -3.0V, Ta=-20 to 75˚C
Min.
—
—
—
Max.
250
4.5
4.5
Unit
ns
s
s
)
4
SED1681F
OA
/D
OA
Timing Chart
16 1
LP
LATCH
DATA
FR
2
3
4
15 16 1
2
3
15 16 1
LP
XSCL
DIO
SHL=V
SS
SEG0
0
1
2
76
77
78
79
0
1
2
3
…
79
0
0
79
SEG79
LP
LATCH
DATA
FR
…
SEG79
SHL=V
DD
SEG0
H L
L
H
L
H
H L
H
H
L
L
H
L
L
H
L
H
V
0
V
2
V
3
V
5
SED1681D
0A
Pad Layout
30
25
20
15
10
5
1
100
35
y
95
x
(0.0)
45
D1681D
0A
50
55
60
65
70
75
80
85
Chip Specification
Chip size
Pad pitch
Chip thickness
Pad size
Dimension [mm]
5.59 3.50
0.160Min.
0.40
±0.025
0.10 0.10
40
90
5
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