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TN0604WG-G

产品描述Power Field-Effect Transistor, 1A I(D), 40V, 1ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, MS-013AC, 12.80 X 7.50 MM, 2.65 MM HEIGHT, GREEN, SOW-20
产品类别分立半导体    晶体管   
文件大小724KB,共6页
制造商Supertex
标准
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TN0604WG-G概述

Power Field-Effect Transistor, 1A I(D), 40V, 1ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, MS-013AC, 12.80 X 7.50 MM, 2.65 MM HEIGHT, GREEN, SOW-20

TN0604WG-G规格参数

参数名称属性值
是否Rohs认证符合
零件包装代码SOIC
包装说明SMALL OUTLINE, R-PDSO-G20
针数20
Reach Compliance Codecompliant
ECCN代码EAR99
其他特性LOW THRESHOLD, LOGIC LEVEL COMPATIBLE
配置SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压40 V
最大漏极电流 (ID)1 A
最大漏源导通电阻1 Ω
FET 技术METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码MS-013AC
JESD-30 代码R-PDSO-G20
JESD-609代码e3
湿度敏感等级1
元件数量1
端子数量20
工作模式ENHANCEMENT MODE
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)NOT SPECIFIED
极性/信道类型N-CHANNEL
最大脉冲漏极电流 (IDM)4 A
认证状态Not Qualified
表面贴装YES
端子面层Matte Tin (Sn)
端子形式GULL WING
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
晶体管应用SWITCHING
晶体管元件材料SILICON
Base Number Matches1

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TN0604
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Low threshold — 1.6V max.
High input impedance
Low input capacitance — 140pF typical
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input
impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
The Quad-Array package (20-Lead SOW (WG)) uses
four independent DMOS transistors which provide four
independent channels.
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Ordering Information
BV
DSS
/BV
DGS
(V)
R
DS(ON)
max
(Ω)
I
D(ON)
min
(A)
V
GS(th)
max
(V)
Package Options
TO-92
TN0604N3-G
-
20-Lead SOW
-
TN0604WG-G
40
40
0.75
1.0
4.0
4.0
1.6
1.6
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Soldering temperature*
Value
BV
DSS
BV
DGS
±20V
-55
O
C to +150
O
C
300
O
C
Pin Configurations
SOURCE
DRAIN
GATE
DRAIN
1
DRAIN
1
DRAIN
1
GATE
1
SOURCE
1
SOURCE
2
GATE
2
DRAIN
2
DRAIN
2
DRAIN
2
DRAIN
4
DRAIN
4
DRAIN
4
GATE
4
SOURCE
4
SOURCE
3
GATE
3
DRAIN
3
DRAIN
3
DRAIN
3
TO-92 (N3)
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
20-Lead SOW (WG)
Product Marking
Top Marking
YYWW
T N 0604WG
LLLLLLLLLL
Product Marking
TN
0604
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
TO-92 (N3)
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
20-Lead SOW (WG)

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