Supertex inc.
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
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Low threshold - 1.6V max.
High input impedance
Low input capacitance - 110pF typical
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
TN0620
General Description
Applications
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This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Ordering Information
Part Number
TN0620N3-G
TN0620N3-G P002
TN0620N3-G P003
TN0620N3-G P005
TN0620N3-G P013
TN0620N3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Product Summary
Packing
1000/Bag
BV
DSS
/BV
DGS
200V
R
DS(ON)
(max)
Package Option
TO-92
I
D(ON)
(min)
V
GS(th)
(max)
6.0Ω
1.0A
1.6V
TO-92
2000/Reel
Pin Configuration
DRAIN
SOURCE
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Value
BV
DSS
BV
DGS
±20V
-55
O
C to +150
O
C
GATE
TO-92
Product Marking
SiTN
06 20
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
TO-92
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Typical Thermal Resistance
Package
TO-92
θ
ja
132
O
C/W
Package may or may not include the following marks: Si or
Doc.# DSFP-TN0620
B080813
Supertex inc.
www.supertex.com
TN0620
Thermal Characteristics
Package
TO-92
(continuous)
I
D
†
(pulsed)
I
D
Power Dissipation
@T
C
= 25
O
C
I
DR
†
250mA
I
DRM
2.0A
250mA
2.0A
1.0W
Notes:
† I
D
(continuous) is limited by max rated T
j
.
Electrical Characteristics
(T
Sym
BV
DSS
V
GS(th)
ΔV
GS(th)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
Parameter
A
= 25
O
C unless otherwise specified)
Min
200
0.6
-
-
-
Typ
-
-
-
-
-
-
-
-
6.0
4.0
-
400
110
40
10
-
-
-
-
-
300
Max
-
1.6
-5.0
100
10
1.0
-
-
8.0
6.0
1.4
-
150
85
35
10
8.0
20
20
1.8
-
Units
V
V
nA
µA
mA
A
Ω
%/
O
C
Conditions
V
GS
= 0V, I
D
= 2.0mA
V
GS
= V
DS
, I
D
= 1.0mA
V
GS
= ± 20V, V
DS
= 0V
V
GS
= 0V, V
DS
= Max Rating
V
DS
= 0.8 Max Rating,
V
GS
= 0V, T
A
= 125°C
V
GS
= 5.0V, V
DS
= 25V
V
GS
= 10V, V
DS
= 25V
V
GS
= 5.0V, I
D
= 250mA
V
GS
= 10V, I
D
= 500mA
V
GS
= 10V, I
D
= 500mA
V
GS
= 0V,
V
DS
= 25V,
f = 1.0MHz
V
DD
= 25V,
I
D
= 1.0A,
R
GEN
= 25Ω
Drain-to-source breakdown voltage
Gate threshold voltage
Change in V
GS(th)
with temperature
Gate body leakage
Zero gate voltage drain current
mV/
O
C V
GS
= V
DS
, I
D
= 1.0mA
-
0.5
1.0
-
-
-
300
-
-
-
-
-
-
-
-
-
On-state drain current
Static drain-to-source on-state resistance
Change in R
DS(ON)
with temperature
Forward transductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Diode forward voltage drop
Reverse recovery time
mmho V
DS
= 25V, I
D
= 500mA
pF
ns
V
ns
V
GS
= 0V, I
SD
= 1.0A
V
GS
= 0V, I
SD
= 1.0A
Notes:
1. All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
90%
10%
t
(ON)
VDD
Pulse
Generator
R
L
OUTPUT
INPUT
0V
t
(OFF)
t
r
t
d(OFF)
t
f
10%
90%
90%
R
GEN
t
d(ON)
VDD
OUTPUT
0V
10%
INPUT
D.U.T.
Doc.# DSFP-TN0620
B080813
2
Supertex inc.
www.supertex.com
TN0620
Typical Performance Curves
4.0
Output Characteristics
4.0
Saturation Characteristics
3.2
3.2
V
GS
= 10V
I
D
(amperes)
I
D
(amperes)
2.4
8V
6V
2.4
V
GS
= 10V
8V
6V
1.6
1.6
4V
0.8
4V
0.8
3V
2V
0
10
20
30
40
50
3V
2V
0
2.0
4.0
6.0
8.0
10
0
0
V
DS
(volts)
V
DS
(volts)
1.0
Transconductance vs. Drain Current
V
DS
= 25V
Power Dissipation vs. Case Temperature
2.0
0.8
G
FS
(siemens)
25
O
150
O
0.4
P
D
(watts)
0.6
T
A
= -55
O
C
1.0
TO-92
0.2
0
0
.05
1.0
1.5
2.0
2.5
0
0
25
50
75
100
125
150
I
D
(amperes)
T
C
( C)
O
10
Maximum Rated Safe Operating Area
Thermal Resistance (normalized)
1.0
Thermal Response Characteristics
0.8
I
D
(amperes)
1.0
TO-92 (DC)
0.6
0.4
0.1
0.2
0.01
T
C
= 25
O
C
1.0
10
100
1000
TO-92
P
D
= 1.0W
T
C
= 25
O
C
0.01
0.1
1.0
10
0
0.001
V
DS
(volts)
Doc.# DSFP-TN0620
B080813
t
P
(seconds)
3
Supertex inc.
www.supertex.com
TN0620
Typical Performance Curves
(cont.)
1.1
BV
DSS
Variation with Temperature
On-Resistance vs. Drain Current
15
12
V
GS
= 5.0V
V
GS
= 10V
BV
DSS
(normalized)
R
DS(ON)
(ohms)
0
50
100
150
9.0
1.0
6.0
3.0
0.9
-50
0
0
0.8
1.6
2.4
3.2
4.0
T
j
( C)
O
I
D
(amperes)
Transfer Characteristics
4.0
V
(th)
and R
DS
Variation with Temperature
2.0
1.4
V
DS
= 25V
3.2
2.4
25
O
C
R
DS
@ 10V, 0.5A
1.0
1.2
1.6
0.8
0.8
0.4
0.6
0.8
150
O
C
0
0
2.0
4.0
6.0
8.0
10
-50
0
50
100
0
150
V
GS
(volts)
T
j
(
O
C)
Capacitance vs. Drain-to-Source Voltage
200
10
Gate Drive Dynamic Characteristics
V
DS
= 10V
f = 1.0MHz
8.0
150
C (picofarads)
C
ISS
100
V
GS
(volts)
6.0
V
DS
= 40V
178 pF
4.0
50
C
OSS
C
RSS
2.0
100 pF
40
0
0
0.5
1.0
1.5
2.0
2.5
0
0
10
20
30
V
DS
(volts)
Q
G
(nanocoulombs)
Doc.# DSFP-TN0620
B080813
4
Supertex inc.
www.supertex.com
R
DS(ON)
(normalized)
T
A
= -55
O
C
V
GS(th)
(normalized)
1.2
V
(th)
@ 1.0mA
1.6
I
D
(amperes)
TN0620
3-Lead TO-92 Package Outline (N3)
D
A
Seating
Plane
1
2
3
L
b
e1
e
c
Front View
Side View
E1
E
1
2
3
Bottom View
Symbol
Dimensions
(inches)
MIN
NOM
MAX
A
.170
-
.210
b
.014
†
-
.022
†
c
.014
†
-
.022
†
D
.175
-
.205
E
.125
-
.165
E1
.080
-
.105
e
.095
-
.105
e1
.045
-
.055
L
.500
-
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#:
DSPD-3TO92N3, Version E041009.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to
http://www.supertex.com/packaging.html.)
Supertex inc.
does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.”
Supertex inc.
does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the
Supertex inc.
(website: http//www.supertex.com)
©2013
Supertex inc.
All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-TN0620
B080813
5
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Supertex inc.
FPGA/CPLD
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