DATA BULLETIN
MX439
Features
•
•
•
•
•
•
1200 Baud MSK Modem
Meets Cellular & Trunked Radio
Specifications
Full-Duplex 1200 Baud
MSK Modem
Document #2048-0041.005 June 1995
Applications
•
•
•
•
Mobile & Cellular Radio Data Signaling
Personal Radio
Portable Data Terminals
General Purpose Applications
On-Chip RX and TX Bandpass Filters
Clock Recovery and Carrier Detect
Pin Selectable Xtal/Clock Frequencies
AVAILABLE
PACKAGES
MX439LH
24-pin PLCC
MX439DW
24-pin SOIC
MX439J: 22 pin CDIP
MX439P: 22 pin PDIP
Figure 1 - Internal Block Diagram
Brief Description
The MX439 is a single-chip CMOS LSI circuit which operates as a 1200 baud MSK modem. The mark and space
frequencies are 1200Hz and 1800Hz phase continuous, and the frequency transitions occur at the zero crossing point.
The transmitter and receiver will work independently, thus providing full-duplex operation at 1200 baud. The baud rate,
transmit mark and space frequencies, and the TX and RX synchronization are all derived from a highly stable Xtal
oscillator. The on-chip oscillator is capable of working at one of two input frequencies: 1.008MHz or 4.032MHz external
Xtal/clock input. Frequency is pin-selectable with the “Clock Rate” logic input. The device includes circuitry for carrier
detect and facility for the RX clock recovery. An on-board switched capacitor 900Hz - 2100Hz bandpass filter provides
optimum carrier filtering. The use of switched capacitor analog filters and digital signal processing results in excellent
dynamic performance with few external components; the CMOS process and current-saving techniques offer low
standby supply current for portable battery-powered applications.
MX439P package discontinued
Pin Number
DW
1
J,P
1
LH
1
Function
Xtal/Clock: The input to an on-chip inverter for use with either a 1.008MHz or a 4.032MHz
Xtal. Alternatively, an external clock may be used. Xtal frequency is selectable on the
“Clock Rate” input pin.
Xtal: Output of the on-chip inverter. (See Figure 2.)
TX Sync O/P: MSK signal centered at a DC level of VBIAS - 0.7V. (See Figure 5.)
TX Signal O/P: With the transmitter disabled, this pin is set to a high impedance state.
When the transmitter is enabled, this pin outputs the 1200/1800Hz MSK signal centered
at a DC level of VBIAS - 0.7 V. (See Figure 5.)
TX Data I/P: Serial logic data to be transmitted is input to this pin and synchronized by
the “TX Sync O/P.” (See Figure 5.)
TX Enable: A logic “1” applied to this input will put the transmitter into powersave while
forcing “TX Sync O/P” to a logic “1” and “TX Signal O/P” to a high impedance state. A logic
“0” will enable the transmitter (See Figure 5). This pin is internally pulled to VDD.
Bandpass O/P: This is the output of the RX 900Hz-2100Hz bandpass filter. The output
impedance of this pin is typically 10kW and may require buffering prior to use.
RX Enable: This is the control of the RX function. The state of other outputs is given
below:
RX Enable
“1”
“0”
RX Function
Enabled
Powersave
Clock Data O/P
Enabled
“0”
Carrier Detect
Enabled
“0”
RX Sync Out
Enabled
“1” or “0”
2
3
5
2
3
5
2
3
5
7
8
6
7
7
8
9
10
8
9
9
10
When both TX and RX functions are disabled, the bias voltage is switched internally to
VSS and Bias pin output impedance is approximately 12.5kW. When the Bias pin is
decoupled by a 1.0mF capacitor (C2) the MX439 may require up to 25ms to establish
correct operation after enabling the RX function. This period may be decreased by either
reducing the value of C2, lowering the Bias pin impedance externally, or adopting a
different powersaving strategy (such as using C2 and C5 and supplying VDD via a series
switch). This pin is internally pulled to VDD.
11
12
13
14
10
11
12
13
11
12
13
14
Bias: Provides bias internally and should be decoupled externally to Vss by capacitor (C2).
(See Fig. 2.)
Vss: Negative supply rail (GND).
Unclocked Data O/P: This pin outputs recovered asynchronous serial data from the
receiver.
Clocked Data O/P: This pin outputs recovered synchronous serial data from the receiver
and is internally latched out by a recovered clock appearing on the “RX Sync O/P” pin.
(See Figure 6.)
Carrier Detect O/P: This pin will output a logic “1” when an MSK signal is being received.
RX Signal I/P: This is the MSK signal input for the receiver. It should be decoupled using
capacitor C3.
RX Sync O/P: This is a flywheel 1200Hz squarewave output which, upon presentation
of the MSK data signal, is synchronized internally to the incoming data. (See Figure 6.)
15
16
18
14
15
17
15
16
18
Page 2
MX439P package discontinued
Inc./Doc.#2048-0041.005
MX439
MX-COM,
Pin Number
DW
21
J,P
19
LH
21
Function
Clock Rate: This logic input selects and allows the use of either a 1.008MHz or 4.032MHz
Xtal/clock input to the on-chip inverter. Logic “1” = 4.032MHz; logic “0” = 1.008MHz. This
input has an internal pulldown resistor (1.008MHz).
Carrier Detect Time Constant (t): This input forms part of the carrier detect integration
function. The value of C4 connected to this pin will affect the carrier detect response time
and hence noise performance. (See Figure 2, Note 3.)
VDD: Positive supply rail. A single 5 volt supply is required.
)
) No Connection.
)
22
20
22
24
22
24
4,6,17
19,20,
23
4,6,17 4,16,
19,20 18,21
23
Note: Output Loading. Large capacitive loads could cause the output pins of this device to oscillate. If capacitive loads in excess
of 200pF are unavoidable, a resistor of (typically) 100W put in series with the load should minimize this effect.
Component References
Component
R1
C1
C2
C3
C4
C5
C6
C7
X1
Tolerances:
Value
1M
33p
1.0μ
0.1μ
0.1μ
1.0μ
1.0μ
33p
1.008MHz
or 4.032 MHz
R = ±10%
C = ±20%
Notes:
1. Bias may be decoupled to V
SS
and V
DD
using C2 and C6 when input signals
are referenced to the bias pin. For input signals referenced to V
SS
, decouple
Bias to V
SS
using C2 only.
2. Use C5 when input signals are referenced to V
SS
to decouple V
DD
.
3. The value of C4 determines the carrier detect time constant. A long time
constant results in improved noise immunity but increased response time. C4
may be varied to trade-off response time for noise immunity.
4. The value of C7 reduces XTAL voltage overshoot. Refer to MX-COM's
Crystal Oscillator Application Note (see Appendix).
5. X1 can be either a 1.008 MHz or 4.032 MHz crystal, depending on the Clock
Rate setting.
Figure 2 - External Component Connections
MX-COM, Inc./Doc.#2048-0041.005
MX439P package discontinued
MX439
Page 3
DIAGRAMS
Figure 3 - Typical Variation of “B.E.R.”
with Input Signal Level
Figure 4 -MX439
Test Set-
up
Figure 5- Transmitter
Timing
Diagram
NOTES:
1.
All timings are related to the TX SYNC OUTPUT.
2.
0.833ms for 1.008MHz or 4.032MHz Xtal.
3.
2ms min. + crystal tolerance.
4.
DC = Don't Care. DV = Data Valid.
Page 4
MX439P package discontinued
Inc./Doc.#2048-0041.005
MX439
MX-COM,
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.
Supply Voltage
Input Voltage at any pin
(ref V
SS
= 0V)
Sink/Source Current (Total)
Total Device Dissipation
@ T
AMB
= 25°C
Derating
Operating Temperature
Storage Temperature
-0.3 to 7.0 V
-0.3 V to V
DD
+ 0.3 V
20mA
800mW max.
10 mW/°C
-40°C to +85°C
-55°C to +125°C
OPERATING LIMITS
All charactistics are measured using the standard test
circuit (Figure 4) with the following test parameters and is
valid for all tests unless otherwise stated:
V
DD
= +5V
T
AMB
= 25°C
Xtal (X1) Frequency: 1.008MHz
0dB reference = 300 mVrms
Noise (band limited 5kHz gaussian white noise)
SNR ratio measured in bit rate bandwidth (1200Hz)
Characteristics
See Note
Static Values
Supply Volts
Supply Current:
RX Enabled, TX Disabled
RX Enabled, TX Enabled
RX Disabled, TX Disabled
Logic “1” level
Logic “0” level
Digital Output Impedance
Analog and Digital Input Impedance
TX Output Impedance
On-Chip Crystal Oscillator:
R
in
R
out
Inverter Gain
Gain Bandwidth Product
Crystal Frequency
Crystal Frequency
Dynamic Values
Receiver:
Signal Input: Dynamic Range (50dB SNR)
Bit Error Rate:
12dB SNR
20dB SNR
Receiver Synchronization 12dB SNR:
Probability of Bit 8 being correct
Probability of Bit 16 being correct
Carrier Detect
Sensitivity
Probability of Carrier Detect being high:
12dB SNR after Bit 8
12dB SNR after Bit 16
0dB Noise (No Signal)
MX-COM, Inc./Doc.#2048-0041.005
Min.
4.5
-
-
-
80%V
DD
-
-
100
-
10
5
10
3 x 10
6
-
-
Typ.
5.0
3.6
4.5
650
-
-
4
-
10
-
-
-
-
1.008
4.032
Max.
5.5
-
-
-
-
20%V
DD
-
-
-
-
15
20
-
-
-
Unit
V
mA
mA
μA
V
V
kΩ
kΩ
kΩ
MΩ
kΩ
dB
MHz
MHz
-
1,9
1,10
2,3
3
3
6
100
-
-
230
7.0
1.0
99
99.5
1000
-
-
-
-
mVrms
10
-4
10
-8
%
%
4
6,7
4,8
4,8
8
-
-
-
-
-
98
99.5
5
125
-
-
-
mVrms
%
%
%
Page 5
MX439P package discontinued
MX439
FPGA/CPLD
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