4 Megabit 5.0 volt-only Sector Erase Flash Memory
KEY FEATURES
•
5.0 V
±
10% Read, Program, and Erase
- Minimizes system-level power requirements
•
High performance
-
45 ns access time
•
Compatible with JEDEC-Standard Commands
- Uses software commands, pinouts, and
packages following industry standards for
single power supply Flash memory
•
Minimum 100,000 Program/Erase Cycles
•
Sector Erase Architecture
- One 16 Kbytes, two 8 Kbytes, one 32 Kbytes,
and seven 64 Kbytes (byte mode)
- Any combination of sectors can be erased
concurrently; also supports full chip erase
•
Erase Suspend/Resume
- Suspend a sector erase operation to allow a
data read in a sector not being erased within
the same device
•
Ready//Busy
- RY//BY output pin for detection of programming
or erase cycle completion
•
/RESET
- Hardware pin resets the internal state machine
to the read mode
•
Internal Erase Algorithms
- Automatically erases a sector, any combination
of sectors, or the entire chip
•
Internal Programming Algorithms
- Automatically programs and verifies data at a
specified address.
•
Low Power Consumption
- 20 mA typical active read current for Byte Mode
- 28 mA typical active read current for Word Mode
- 30 mA typical program/erase current
•
Sector Protection
- Hardware method disables any combination
of sectors from a program or erase operation
•
Boot Code Sector Architecture
HY29F400A Series
DESCRIPTION
The HY29F400A is an 4 Megabit, 5.0 volt-only CMOS
Flash memory device organized as a 512 Kbytes of 8-
bits each, or 256 Kbytes of 16 bits each. The device
is offered in standard 44-pin PSOP and 48-pin
TSOP packages. It is designed to be programmed
and erased in-system with a 5.0 volt power-supply
and can also be programmed in standard PROM
programmers.
With access times of 45ns, 55ns, 70ns, 90 ns, 120
ns and 150 ns, the HY29F400A has separate chip
enable (/CE), write eable (/WE), and output enable (/
OE) controls. Hyundai Flash memory devices re-
liably store memory data even after 100,000 pro-
gram/erase cycles.
The HY29F400A is entirely pin and command set
compatible with the JEDEC standard for 4Mega-
bit Flash memory devices. Commands are writ-
ten to the command register using standard mi-
croprocessor write timings. Register contents
serve as input to an internal state-machine that
controls the erase and programming circuitry.
Write cycles also internally latch addresses and
data needed for the programming and erase
operations.
The HY29F400A is programmed by executing the
program command sequence. This will start the
internal byte/word programming algorithm that
automatically times the program pulse widths
and also verifies proper cell margin. Erase is ac-
complished by executing either the sector erase
or chip erase command sequence. This will start
the internal erasing algorithm that automatically
times the erase pulse width and also verifies
proper cell margin. No preprogramming is re-
quired prior to execution of the internal erase al-
gorithm. Sectors of the HY29F400A Flash
memory array are electrically erased via Fowler-
Nordheim tunneling. Bytes/words are pro-
grammed one byte/word at a time using a hot
electron injection mechanism.
The HY29F400A features a sector erase architec-
ture. The device memory array is divided into one
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and
seven 64 Kbytes. Sectors can be erased indi-
vidually or in groups without affecting the data in
other sectors. Multiple sector erase and full chip
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits
described. No patent licences are implied.
Rev.03/Aug.97
Hyundai Semiconductor
erase capabilities add flexibility to altering the data in
the device. To protect this data from accidental
program and erase, the device also has a sector
protect function. This function hardware write pro-
tects the selected sector(s). The sector protect
and sector unprotect features can be enabled in
a PROM programmer.
For read, program and erase operation, the
HY29F400A needs a single 5.0 volt power-supply.
Internally generated and well regulated voltages
are provided for the program and erase
operation. A low Vcc detector inhibits write opera-
tions on loss of power. End of program or erase is
detected by the Ready/Busy status pin, /Data Polling
of DQ7, or by the Toggle Bit I feature on DQ6.
Once the program or erase cycle has been suc-
cessfully completed, the device internally resets to
the Read mode.
The HY29F400A also has a hardware /RESET pin.
Driving the /RESET pin low during execution of an
Internal Programming or Erase command will ter-
minate the operation and reset the device to the Read
mode. The /RESET pin may be tied to the system
reset circuitry, so that the system will have ac-
cess to boot code upon completion of system
reset, even if the Flash device is in the process
of an Internal Programming or Erase operation. If
the device is reset using the /RESET pin during an
Internal Programming or Erase operation, data
in the address locations on which the internal state
machine is operating will be erroneous. Thus,
these address locations will need rewriting after
the device is reset.
BLOCK DIAGRAM
RY/BY
Buffer
RY/BY
Erase Voltage
Generator
DQ0-DQ15
Input/Output
Buffer
Vcc
Vss
/WE
/BYTE
/RESET
State
Control
Command
Register
PGM Voltage
Generator
/CE
/OE
Chip Enable
Output Enable
Logic
STB
STB
Data Latch
Y-Decoder
Address
Latch X-Decoder
Y-Gating
Cell Matrix
Vcc Detector
Timer
A0-A17
A-1
HY29F400A
2
BUS OPERATION
Table 1. Bus Operations (/BYTE = V
IH
)
(1)
OPERATION
Electronic ID Manufacturer
(2)
Electronic ID Device
Read
(3)
Standby
Hardware RESET
Output Disable
Write
Enable Sector Protect
Verify Sector Protect
(2)
Temporary Sector Unprotect
(2)
/CE
L
L
L
H
X
L
L
L
L
X
/OE
L
L
L
X
X
H
H
V
ID
L
X
/WE
H
H
H
X
X
H
L
L
H
X
A0
L
H
A0
X
X
X
A0
X
L
A0
A1
L
L
A1
X
X
X
A1
X
H
A1
A6
L
L
A6
X
X
X
A6
X
L
A6
A9
V
ID
V
ID
A9
X
X
X
A9
V
ID
V
ID
A9
DQ0-DQ15
Code
Code
D
OUT
High Z
High Z
High Z
D
IN(4)
X
Code
D
IN
/RESET
H
H
H
H
L
H
H
H
H
V
ID
Notes:
1. L = V
IL
, H = V
IH
, X = Don't Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3. /WE can be V
IL
if /CE is V
IL
, /OE at V
IH
initiates the write operations.
4. Refer to Table 6 for valid D
IN
during a write operation.
Table 2. Bus Operations (/BYTE = V
IL
)
(1)
OPERATION
Electronic ID Manufacturer
Electronic ID Device
(2)
Read
(3)
Standby
Hardware RESET
Output Disable
Write
Enable Sector Protect
Verify Sector Protect
(2)
Temporary Sector Unprotect
(2)
/CE
L
L
L
H
X
L
L
L
L
X
/OE
L
L
L
X
X
H
H
V
ID
L
X
/WE
H
H
H
X
X
H
L
L
H
X
A0
L
H
A0
X
X
X
A0
X
L
A0
A1
L
L
A1
X
X
X
A1
X
H
A1
A6
L
L
A6
X
X
X
A6
X
L
A6
A9
V
ID
V
ID
A9
X
X
X
A9
V
ID
V
ID
A9
DQ0-DQ7 DQ8-DQ15
Code
Code
D
OUT
High Z
High Z
High Z
D
IN(4)
X
Code
D
IN
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
X
/RESET
H
H
H
H
L
H
H
H
H
V
ID
Notes:
1. L = V
IL
, H = V
IH
, X = Don't Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3. /WE can be V
IL
if /CE is V
IL
, /OE at V
IH
initiates the write operations.
4. Refer to Table 6 for valid D
IN
during a write operation.
HY29F400A
4
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