A3959
DMOS Full-Bridge PWM Motor Driver
Features and Benefits
▪
±3 A, 50 V Output Rating
▪
Low r
DS(on)
Outputs (270 m, Typical)
▪
Mixed, Fast, and Slow Current-Decay Modes
▪
Synchronous Rectification for Low Power Dissipation
▪
Internal UVLO and Thermal-Shutdown Circuitry
▪
Crossover-Current Protection
▪
Internal Oscillator for Digital PWM Timing
Description
Designed for pulse width modulated (PWM) current control of
DC motors, the A3959 is capable of output currents to ±3 A and
operating voltages to 50 V. Internal fixed off-time PWM current-
control timing circuitry can be adjusted via control inputs to
operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use
in controlling the speed and direction of a DC motor with
externally applied PWM-control signals. Internal synchronous
rectification control circuitry is provided to reduce power
dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge
pump, and crossover-current protection. Special power-up
sequencing is not required.
The A3959 provides a choice of three power packages, a 24-pin
DIP with batwing tabs (package suffix ‘B’), a 24-lead SOIC
with four internally-fused pins (package suffix ‘LB’), and a
thin (<1.2 mm) 28-pin TSSOP with an exposed thermal pad
(suffix ‘LP’). In all cases, the power pins and tabs are at ground
potential and need no electrical isolation. Each package is lead
(Pb) free, with 100% matte tin leadframes.
Packages:
Package B, 24-pin DIP
with exposed tabs
Package LB, 24-pin SOIC
with internally fused pins
Package LP, 28-pin TSSOP
with exposed thermal pad
Not to scale
Functional Block Diagram
V
DD
LOGIC
SUPPLY
CHARGE PUMP
BANDGAP
V
DD
C
REG
TSD
V
BB
+
LOAD
SUPPLY
BANDGAP
REGULATOR
V
REG
CP1
CP2
CP
TO V
DD
UNDER-
VOLTAGE &
FAULT DETECT
CHARGE
PUMP
SLEEP
OUT
A
CONTROL LOGIC
GATE DRIVE
EXT MODE
PHASE
ENABLE
OUT
B
SENSE
ZERO
CURRENT
DETECT
TO V
DD
BLANK
PFD1
PFD2
ROSC
PWM
TIMER
OSC
C
S
R
S
CURRENT
SENSE
REFERENCE
BUFFER &
10
REF
V
REF
Dwg. FP-048-2A
29319.37L
A3959
DMOS Full-Bridge PWM Motor Driver
Selection Guide
Part Number
A3959SB-T
A3959SLBTR-T
A3959SLPTR-T
Package
24-pin DIP with exposed tabs
24-pin SOIC with internally fused pins
28-pin TSSOP with exposed thermal pad
Packing
15 per tube
1000 per reel
4000 per reel
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Logic Supply Voltage
Input Voltage
Sense Voltage
Reference Voltage
Output Current
Package Power Dissipation
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
Symbol
V
BB
V
DD
V
IN
V
S
V
REF
I
OUT
P
D
T
A
T
J
(max)
T
stg
Output current rating may be limited by duty cycle, am-
bient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating
or a junction temperature of 150°C.
See Thermal Characteristics
Range S
Fault conditions that produce excessive junction temperature will activate
the device’s thermal shutdown circuitry. These conditions can be toler-
ated but should be avoided.
Repetitive
Peak, < 3
μs
Continuous
t
w
< 30 ns
Continuous
t
w
< 3
μs
Notes
Rating
50
7.0
–0.3 to V
DD
+ 0.3
–1.0 to V
DD
+ 1.0
0.5
2.5
V
DD
±3.0
±6.0
–
–20 to 85
150
–55 to 150
Units
V
V
V
V
V
V
V
A
A
–
ºC
ºC
ºC
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3959
Thermal Characteristics
Characteristic
Symbol
DMOS Full-Bridge PWM Motor Driver
Test Conditions
B package
Value
3.3
2.5
3.1
Units
W
W
W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
Package Power Dissipation
P
D
LB package
LP package
1-layer PCB, minimal exposed copper area
B Package
2
2-layer PCB, 1-in. 2-oz copper exposed area
54
36
26
77
51
35
100
40
28
6
2
4-layer PCB, based on JEDEC standard
1-layer PCB, minimal exposed copper area
Package Thermal Resistance, Junction
to Ambient
R
θJA
LB Package
2
2-layer PCB, 1-in. 2-oz copper exposed area
4-layer PCB, based on JEDEC standard
1-layer PCB, minimal exposed copper area
LP Package
2
2-layer PCB, 1-in. 2-oz copper exposed area
4-layer PCB, based on JEDEC standard
Package Thermal Resistance, Junction
to Tab
Package Thermal Resistance, Junction
to Pad
R
θJT
R
θJP
B and LB packages
LP package
*Additional thermal information available on Allegro website.
5
ALLOWABLE PACKAGE POWER DISSIPATION (W)
4
SUFFIX 'B', R
JA
= 26 C/W
SUFFIX 'LP', R
JA
= 28 C/W
SUFFIX 'LB', R
JA
= 35 C/W
4-LAYER BOARD
3
2
1
SUFFIX 'B', R
0
JA
= 36 C/W
SUFFIX 'LP', R
JA
= 40 C/W
SUFFIX 'LB', R
JA
= 51 C/W
2-LAYER BOARD,
1 SQ. IN. COPPER EA. SIDE
25
50
75
100
TEMPERATURE IN C
125
150
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3959
DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise)
Characteristics
Output Drivers
Load Supply Voltage Range
Output Leakage Current
Output On Resistance
Crossover Delay
Body Diode Forward Voltage
V
F
Source diode, I
F
= -3 A
Sink diode, I
F
= 3 A
f
PWM
< 50 kHz
Load Supply Current
Control Logic
Logic Supply Voltage Range
Logic Input Voltage
Logic Input Current
(all inputs except ENABLE)
Logic Supply Current
ENABLE Input Current
Internal OSC frequency
Reference Input Volt. Range
Reference Input Current
Comparator Input Offset Voltage
V
DD
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
I
DD
I
IN(1)
I
IN(0)
f
OSC
V
REF
I
REF
V
IO
V
IN
= 2.0 V
V
IN
= 0.8 V
f
PWM
< 50 kHz
Sleep mode
V
IN
= 2.0 V
V
IN
= 0.8 V
ROSC shorted to GROUND
ROSC = 51 kΩ
Operating
V
REF
= V
DD
V
REF
= 0 V
Operating
4.5
2.0
–
–
–
–
–
–
–
3.25
3.65
0.0
–
–
5.0
–
–
<1.0
<-2.0
6.0
–
40
16
4.25
4.25
–
–
±5.0
5.5
–
0.8
20
-20
10
2.0
100
40
5.25
4.85
V
DD
±1.0
–
V
V
V
μA
μA
mA
mA
μA
μA
MHz
MHz
V
μA
mV
I
BB
Charge pump on, outputs disabled
Sleep mode
V
BB
I
DSS
r
DS(on)
Operating
During sleep mode
V
OUT
= V
BB
V
OUT
= 0 V
Source driver, I
OUT
= -3 A
Sink driver, I
OUT
= 3 A
9.5
0
–
–
–
–
300
–
–
–
–
–
–
–
<1.0
<-1.0
270
270
600
–
–
4.0
2.0
–
50
50
20
-20
300
300
1000
1.6
1.6
7.0
5.0
20
V
V
μA
μA
mΩ
mΩ
ns
V
V
mA
mA
μA
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Continued next page …
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3959
DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS (continued) at T
A
= +25°C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise)
Characteristics
Reference Divider Ratio
Gm Error
(Note 3)
Symbol
–
E
Gm
V
REF
= V
DD
V
REF
= 0.5 V
0.5 E
in
to 0.9 E
out
:
PWM change to source on
Propagation Delay Times
t
pd
PWM change to source off
PWM change to sink on
PWM change to sink off
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
NOTES:
Test Conditions
Min.
–
–
–
600
50
600
50
–
–
Typ.
10
–
–
750
150
750
100
165
15
4.2
0.10
Max.
–
±4.0
±14
1200
350
1200
150
–
–
4.45
–
Units
–
%
%
ns
ns
ns
ns
°C
°C
V
V
T
J
∆T
J
UVLO
∆UVLO
Increasing V
DD
3.90
0.05
1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. G
m
error = ([V
REF
/10] – V
SENSE
)/(V
REF
/10) where V
SENSE
= I
TRIP
•R
S
.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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