®
X9520
Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
Data Sheet
August 20, 2007
FN8206.2
Triple DCP, POR, 2kbit EEPROM Memory,
Dual Voltage Monitors
The X9520 combines three Digitally Controlled
Potentiometers (DCPs), V1/VCC Power-on Reset (POR)
circuitry, two programmable voltage monitor inputs with
software and hardware indicators, and integrated EEPROM
with Block Lock™ protection. All functions of the X9520 are
accessed by an industry standard 2-Wire serial interface.
Two of the DCPs of the X9520 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber Optic
module. The third DCP may be used to set other various
reference quantities, or as a coarse trim for one of the other two
DCPs. The 2kbit integrated EEPROM may be used to store
module definition data. The programmable POR circuit may be
used to ensure that V1/VCC is stable before power is applied to
the laser diode/module. The programmable voltage monitors
may be used for monitoring various module alarm levels.
The features of the X9520 are ideally suited to simplifying the
design of fiber optic modules which comply to the Gigabit
Interface Converter (GBIC) specification. The integration of
these functions into one package significantly reduces board
area, cost and increases reliability of laser diode modules.
Features
• Three Digitally Controlled Potentiometers (DCPs)
- 64 Tap - 10kΩ
- 100 Tap - 10kΩ
- 256 Tap - 100kΩ
- Nonvolatile
- Write Protect Function
• 2kbit EEPROM Memory with Write Protect & Block Lock
™
• 2-Wire Industry Standard Serial Interface
- Complies to the Gigabit Interface Converter (GBIC)
specification
• Power-on Reset (POR) Circuitry
- Programmable Threshold Voltage
- Software Selectable Reset Timeout
- Manual Reset
• Two Supplementary Voltage Monitors
- Programmable Threshold Voltages
• Single Supply Operation
- 2.7V to 5.5V
• Hot Pluggable
• 20 Ld Package
- TSSOP
• Pb-free available (RoHS compliant)
Ordering Information
PART NUMBER
X9520V20I-A
X9520V20I-AT1*
X9520V20I-AT2*
X9520V20I-B
X9520V20I-BT1*
X9520V20IZ-A (Note)
X9520V20IZ-AT1* (Note)
X9520V20IZ-AT2* (Note)
X9520V20IZ-B (Note)
X9520V20IZ-BT1* (Note)
PART
MARKING
X9520V IA
X9520V IA
X9520V IA
X9520V IB
X9520V IB
X9520V ZIA
X9520V ZIA
X9520V ZIA
X9520V ZIB
X9520V ZIB
PRESET (FACTORY SHIPPED) TRIPx
THRESHOLD LEVELS (x = 2, 3)
Optimized for 3.3V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 5V system monitoring**
Optimized for 5V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 5V system monitoring**
Optimized for 5V system monitoring**
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
PKG.
DWG. #
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
* Please refer to TB347 for details on reel specifications.
** For details, see DC Operating characteristics
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9520
Block Diagram
R
H0
WIPER
COUNTER
REGISTER
R
W0
R
L0
8
WP
PROTECT LOGIC
6 - BIT
NONVOLATILE
MEMORY
CONSTAT
R
H1
WIPER
COUNTER
REGISTER
SDA
SCL
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
4
REGISTER
R
W1
R
L1
2kbit
7 - BIT
NONVOLATILE
MEMORY
EEPROM
ARRAY
WIPER
COUNTER
REGISTER
R
H2
R
W2
R
L2
2
8 - BIT
NONVOLATILE
MEMORY
THRESHOLD
RESET LOGIC
MR
V3
VTRIP
3
-
+
-
+
+
-
POWER-ON /
LOW VOLTAGE
RESET
GENERATION
V3RO
V2
VTRIP
2
V2RO
V1/VCC
VTRIP
1
V1RO
Detailed Device Description
The X9520 combines three Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/VCC power-on reset
control, V1/VCC low voltage reset control, two
supplementary voltage monitors, and integrated EEPROM
with Block Lock™ protection, in one package. These
functions are suited to the control, support, and monitoring of
various system parameters in Fiber Channel/Gigabit
Ethernet fiber optic modules, such as in Gigabit Interface
Converter (GBIC) applications. The combination of the
X9520 fucntionality lowers system cost, increases reliability,
and reduces board space requirements using Intersil’s
unique XBGA™ packaging.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents. One lower resolution
DCP may be used for setting sundry system parameters
such as maximum laser output power (for eye safety
requirements).
Applying voltage to V
CC
activates the Power-on Reset circuit
which allows the V1RO output to go HIGH, until the supply
the supply voltage stabilizes for a period of time (selectable
via software). The V1RO output then goes LOW. The Low
Voltage Reset circuitry allows the V1RO output to go HIGH
when V
CC
falls below the minimum V
CC
trip point. V1RO
remains HIGH until V
CC
returns to proper operating level. A
Manual Reset (MR) input allows the user to externally trigger
the V1RO output (HIGH).
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware output
(V3RO, V2RO) are allowed to go HIGH. If the input voltage
becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding binary
representation of the two monitor circuit outputs (V2RO and
V3RO) are also stored in latched, volatile (CONSTAT)
register bits. The status of these two monitor outputs can be
read out via the 2-wire serial port.
An application of the V1RO output may be to drive the
“ENABLE” input of a Laser Driver IC, with MR as a
“TX_DISABLE” input. V2RO and V3RO may be used to
monitor “TX_FAULT” and “RX_LOS” conditions respectively.
Intersil’s unique circuits allow for all internal trip voltages to
be individually programmed with high accuracy. This gives
the designer great flexibility in changing system parameters,
either at the time of manufacture, or in the field.
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s Block Lock™ protection. This
memory may be used to store fiber optic module
manufacturing data, serial numbers, or various other system
parameters. The EEPROM array is internally organized as x
8, and utilizes Intersil’s proprietary Direct Write™ cells,
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
The device features a 2-Wire interface and software protocol
allowing operation on an I
2
C™ compatible serial bus.
2
FN8206.2
August 20, 2007
X9520
Pinout
X9520
(20 LD TSSOP)
TOP VIEW
R
H2
R
W2
R
L2
V3
V3RO
MR
WP
SCL
SDA
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V1/VCC
V1RO
V2RO
V2
R
L0
R
W0
R
H0
R
H1
R
W1
R
L1
NOT TO SCALE
Pin Descriptions
TSSOP
1
2
3
4
5
NAME
R
H2
R
w2
R
L2
V3
V3RO
FUNCTION
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the
V
TRIP3
threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to V
SS
when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than V
TRIP3
and goes LOW
when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external “pull-up”
resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin
(V1/VCC RESET Output pin). V1RO will remain HIGH for time t
purst
after MR has returned to it’s normally LOW state. The
reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external
“pull-down” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock
feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed
in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin
uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input
buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the
V
TRIP2
threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to V
SS
when not used.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than V
TRIP2
, and goes LOW
when V2 is less than V
TRIP2
. There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an
external “pull-up” resistor.
6
MR
7
WP
8
9
10
11
12
13
14
15
16
17
18
SCL
SDA
Vss
R
L1
R
w1
R
H1
R
H0
R
W0
R
L0
V2
V2RO
3
FN8206.2
August 20, 2007
X9520
Pin Descriptions
(Continued)
TSSOP
19
NAME
V1RO
FUNCTION
V1/VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever V1/VCC falls below
V
TRIP1
. V1RO becomes active on power-up and remains active for a time t
purst
after the power supply stabilizes (t
purst
can
be changed by varying the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an external
“pull-up” resistor. The V1RO pin can be forced active (HIGH) using the manual reset (MR) input pin.
20
V1/VCC Supply Voltage.
Principles of Operation
Serial Interface
SERIAL INTERFACE CONVENTIONS
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the X9520 operates as a slave in all applications.
SERIAL CLOCK AND DATA
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions. See Figure 1.
On power-up of the X9520, the SDA pin is in the input mode.
SERIAL START CONDITION
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met. See Figure 2.
SERIAL STOP CONDITION
All communications must be terminated by a STOP condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH.
The STOP condition is also used to place the device into the
Standby power mode after a read sequence. A STOP
condition can only be issued after the transmitting device has
released the bus. See Figure 2.
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 1. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
START
STOP
FIGURE 2. VALID START AND STOP CONDITIONS
4
FN8206.2
August 20, 2007
X9520
SCL from
SCL
Master
from
Master
Data Output from
Transmitter
1
8
9
Data Output from
Receiver
START
ACKNOWLEDGE
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
SERIAL ACKNOWLEDGE
An ACKNOWLEDGE (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to ACKNOWLEDGE that it received the eight
bits of data. Refer to Figure 3.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent eight
bit word.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected and
no STOP condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an ACKNOWLEDGE is not
detected. The master must then issue a STOP condition to
place the device into a known state.
Device Internal Addressing
Addressing Protocol Overview
The user addressable internal components of the X9520 can
be split up into three main parts:
• Three Digitally Controlled Potentiometers (DCPs)
• EEPROM array
• Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each of
these individual parts, a 1, 2 or 3 Byte protocol is used. All
operations however must begin with the Slave Address Byte
being issued on the SDA pin. The Slave address selects the
part of the X9520 to be addressed, and specifies if a Read or
Write operation is to be performed.
It should be noted that in order to perform a write operation
to either a DCP or the EEPROM array, the Write Enable
Latch (WEL) bit must first be set (See “BL1, BL0: Block Lock
protection bits - (Nonvolatile)” on page 13.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4). This byte consists of
three parts:
• The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4). The
Device Type Identifier must always be set to 1010 in order
to select the X9520.
• The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111 selects
the DCP structures in the X9520. The CONSTAT Register
may be selected using the Internal Device Address 010.
• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined in
the bits SA3 - SA1). When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation
(Refer to Figure 4.)
5
FN8206.2
August 20, 2007
FPGA/CPLD
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