January 2002
Advance information
AS6VB51216
2.7V to 3.3V 512K X 16 Intelliwatt
TM
Super Low-Power CMOS SRAM
Features
•
•
•
•
•
•
•
AS6VB51216
Intelliwatt™ active power circuitry
Industrial and commercial temperature ranges available
Organization: 524,288 words × 16 bits
2.7V to 3.3V power supply range
Fast access time of 55 ns
Low power consumption: ACTIVE
- 132 mW max at 3.3V and 55 ns
- 66 µW max at 3.3V
• 1.5V data retention
• Equal access and cycle times
• Easy memory expansion with CS1,
CS2
, OE inputs
• Smallest footprint packages
- 48-ball FBGA; 7.0 x 9.0 mm
• ESD protection
≥
2000 volts
• Latch-up current
≥
200 mA
• Low power consumption: STANDBY
Logic block diagram
Row Decoder
V
DD
512K × 16
Array
(8,388,608)
V
SS
Pin arrangement (top view)
48-CSP Ball-Grid-Array Package
I/O0–I/O7
I/O8–I/O15
WE
I/O
buffer
Control circuit
Column decoder
A
B
C
D
E
F
G
H
'18
1
LB
I/O8
I/O9
V
SS
V
CC
I/O14
I/O15
A18
2
3
OE
A0
UB
A3
I/O10 A5
I/O11 A17
I/O12 V
SS
I/O13 A14
NC
A12
A8
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CS
I/O1
I/O3
I/O4
I/O5
WE
A11
6
CS2
I/O0
I/O2
V
CC
V
SS
I/O6
I/O7
DNU
1
A0~A8
'R 1RW 8VH
A9~A18
UB
OE
LB
CS1
CS2
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V
CC
Range
Product
AS6VB51216-55
AS6VB51216-70
AS6VB51216-85
Min
(V)
2.7
2.7
2.7
Typ
2
(V)
3.0
3.0
3.0
Max
(V)
3.3
3.3
3.3
Speed
(ns)
55
70
85
Power Dissipation
Operating (I
CC1
)
Max (mA)
4
4
4
Standby (I
SB2
)
Max (
µ
A)
25
25
25
1/21/02; V.0.9.6
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
AS6VB51216
Functional description
The AS6VB51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288
words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55/70/85 ns are ideal for low-power applications. Active high and low
chip enables (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems.
When CS1 is high or CS2 is low, or UB and LB are high, the device enters standby mode: the AS6VB51216 is guaranteed not to
exceed 66
µ
W power consumption at 3.3V. The device also retains data when V
CC
is reduced to 1.5V for even lower power
consumption.
The device can also be put into standby mode when deselected (CS1 is high or CS2 is low, or UB and LB are high). The input/
output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CS1 is high or CS2 is low, or UB and
LB are high), outputs are disabled (OE High), UB and LB are disabled (UB, LB High), or during a write operation ( CS1 is low or
CS2 is high and WE Low).
Writing to the device is accomplished by taking Chip Enables CS1 Low, CS2 High and Write Enable (WE) input Low. If Byte Low
Enable (LB) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0
through A18). If Byte High Enable (UB) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location spec-
ified on the address pins (A0 through A18). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
Reading from the device is accomplished by taking Chip Enable CS1 Low, CS2 High and Output Enable (OE) Low while forcing
the Write Enable (WE) High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (UB) is Low, then data from memory will appear on I/O8 to I/O15.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the
JEDEC 48-ball FBGA package.
$EVROXWH PD[LPXP UDWLQJV
Parameter
Voltage on V
CC
relative to V
SS
Voltage on any I/O pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with V
CC
applied
DC output current (low)
Symbol
V
tIN
V
tI/O
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
Max
V
CC
+ 0.5
V
CC
+ 0.5
1.0
+150
+125
20
Unit
V
V
W
°
C
°
C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
1/21/02; V.0.9.6
Alliance Semiconductor
P. 2 of 10
AS6VB51216
Capacitance
(f = 1 MHz, T
a
= Room temperature, V
CC
= NOMINAL)
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
–55
Parameter
Read cycle time
Address access time
Chip enable (CS) access time
Output enable (OE) access time
Output hold from address change
CS
ORZ W
o output in low Z
CS high to output in high Z
OE low to output in low Z
UB/LB access time
UB/LB low to low Z
UB/LB high to high Z
OE high to output in high Z
Power up time
Power down time
Signals
A, CS, CS2, WE, OE, LB, UB
I/O
–70
Max
–
55
55
25
–
–
20
–
55
–
20
20
–
55
Min
70
–
–
–
10
10
0
5
–
10
0
0
0
–
Max
–
70
70
35
–
–
25
–
70
–
25
25
–
70
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
–85
Min
85
–
–
–
10
10
0
5
–
10
0
0
0
–
Max
–
85
85
35
–
–
25
–
85
–
25
25
–
85
Max
5
7
Unit
pF
pF
Read cycle (over the operating range)
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
BA
t
BLZ
t
BHZ
t
OHZ
t
PU
t
PD
Min
55
–
–
–
10
10
0
5
–
10
0
0
0
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
4, 5
4, 5
5
4, 5
4, 5
4, 5
3
3
Notes
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)
(CS1=OE=LB=UB=Low, CS2=High)
t
RC
Address
t
OH
D
OUT
Previous data valid
t
AA
Data valid
t
OH
1/21/02; V.0.9.6
Alliance Semiconductor
P. 4 of 10
AS6VB51216
Read waveform 2 (CS1, CS2, OE, UB, LB controlled)
[WE=High]
t
RC
Address
t
AA
OE
t
OLZ
CS1
t
ACS
t
OHZ
t
OE
t
OH
CS2
t
LZ
LB, UB
t
BLZ
D
OUT
t
BA
Data valid
t
BHZ
t
HZ
Write cycle (over the operating range)
–55
Parameter
Write cycle time
Chip enable to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
UB/LB low to end of write
–70
Max
–
–
–
–
–
–
–
–
20
–
–
Min
70
60
60
0
50
0
30
0
0
5
60
Max
–
–
–
–
–
–
–
–
20
–
–
Min
85
60
60
0
50
0
30
0
0
5
60
–85
Max
–
–
–
–
–
–
–
–
20
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
12
12
Notes
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
Min
55
45
45
0
40
0
25
0
0
5
45
1/21/02; V.0.9.6
Alliance Semiconductor
P. 5 of 10
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