RMS phase jitter at: 250MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.23ps (typical)
Full 3.3V or 2.5V output supply modes
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Frequency Table
Inputs
Crystal Frequency (MHz)
25
M
20
N
2
Multiplication Value M/N
10
Output Frequency (MHz)
250
Block Diagram
OE
Pullup
Pin Assignment
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
OE
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
N = ÷2
(fixed)
Q
nQ
M = ÷20
(fixed)
ICS842023
8 Lead TSSOP
4.40mm x 3.0mm x 0.925 package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
HSTL CLOCK GENERATOR
1
ICS842023AG REV. B JULY 15, 2008
ICS842023
FEMTOCLOCK™CRYSTAL-TO-HSTL CLOCK GENERATOR
PRELIMINARY
.
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT
XTAL_IN
OE
nQ, Q
V
DD
Power
Power
Input
Input
Output
Power
Pullup
Type
Description
Analog supply pin.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Output enable pin. When HIGH, Q/nQ outputs are active. When LOW, the
Q/nQ outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Differential output pair. HSTL interface levels.
Core supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Ω
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
129.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Power Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
89
9
Units
V
V
mA
mA
IDT™ / ICS™
HSTL CLOCK GENERATOR
2
ICS842023AG REV. B JULY 15, 2008
ICS842023
FEMTOCLOCK™CRYSTAL-TO-HSTL CLOCK GENERATOR
PRELIMINARY
Table 3B. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Power Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
84
8
Units
V
V
mA
mA
Table 3C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
OE
OE
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 3D. HSTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
1.0
0
40
0.4
Typical
Maximum
1.8
0.6
60
1.8
Units
V
V
%
V
NOTE 1: Outputs terminated with 50Ω to GND.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 3E. HSTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
40
0.6
Test Conditions
Minimum
1.0
Typical
Maximum
1.4
0.4
60
1.4
Units
V
V
%
V
NOTE 1: Outputs terminated with 50Ω to GND.
NOTE 2: Defined with respect to output voltage swing at a given condition.
IDT™ / ICS™
HSTL CLOCK GENERATOR
3
ICS842023AG REV. B JULY 15, 2008
ICS842023
FEMTOCLOCK™CRYSTAL-TO-HSTL CLOCK GENERATOR
PRELIMINARY
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
24.5
Test Conditions
Minimum
Typical
Fundamental
34
50
7
MHz
Maximum
Units
Ω
pF
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Parameter
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Symbol
Output Frequency
RMS Phase Jitter, Random;
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
250MHz
Integration Range: 1.875MHz – 20MHz
20% to 80%
200
47
Test Conditions
Minimum
245
0.23
700
53
Typical
Maximum
340
Units
MHz
ps
ps
%
NOTE 1: Please refer to Phase Noise Plots.
Table 5B. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Parameter
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Symbol
Output Frequency
RMS Phase Jitter, Random;
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
250MHz
Integration Range: 1.875MHz – 20MHz
20% to 80%
200
47
Test Conditions
Minimum
245
0.32
700
53
Typical
Maximum
340
Units
MHz
ps
ps
%
NOTE 1: Please refer to Phase Noise Plots.
IDT™ / ICS™
HSTL CLOCK GENERATOR
4
ICS842023AG REV. B JULY 15, 2008
ICS842023
FEMTOCLOCK™CRYSTAL-TO-HSTL CLOCK GENERATOR
PRELIMINARY
Parameter Measurement Information
3.3V±5%
3.3V±5%
2.5V±5%
2.5V±5%
V
DD
V
DDA
Qx
SCOPE
V
DD
V
DDA
Qx
SCOPE
HSTL
GND
nQx
HSTL
GND
nQx
0V
0V
3.3V HSTL Output Load AC Test Circuit
2.5V HSTL Output Load AC Test Circuit
Phase Noise Plot
nQ
Noise Power
Q
t
PW
Phase Noise Mask
t
PERIOD
odc =
f
1
Offset Frequency
f
2
t
PW
t
PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
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