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Spartan-IIE 1.8V FPGA
Automotive XA Product Family:
Introduction and Ordering
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DS106-1 (v2.0) August 9, 2013
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Product Specification
•
•
Guaranteed to meet full electrical specifications over
T
J
= –40°C to +125°C
Second generation ASIC replacement technology
- Densities as high as 6,912 logic cells with up to
300,000 system gates
- Very low cost
System-level features
- SelectRAM+™ hierarchical memory:
·
16 bits/LUT distributed RAM
·
Configurable 4K-bit true dual-port block RAM
·
Fast interfaces to external RAM
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
·
Eliminate clock distribution delay
·
Multiply, divide, or phase shift
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
- Low-cost packages available in all densities
- 19 high-performance interface standards
·
LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
·
LVDS and LVPECL differential I/O
- Up to 120 differential I/O pairs that can be input,
output, or bidirectional
Fully supported by powerful Xilinx ISE development
system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools
- Extensive IP library including DSP functions
Introduction
The Xilinx Automotive (XA) Spartan™-IIE 1.8V Field-Pro-
grammable Gate Array family is specifically designed to
meet the needs of high-volume, cost-sensitive automotive
electronic applications. The family gives users high perfor-
mance, abundant logic resources, and a rich feature set, all
at an exceptionally low price. The five-member family offers
densities ranging from 50,000 to 300,000 system gates, as
shown in
Table 1.
System performance is supported beyond
200 MHz.
Spartan-IIE devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined architecture based on
the proven Virtex™-E platform. Features include block RAM
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable
I/O standards, and four DLLs (Delay-Locked Loops). Fast,
predictable interconnect means that successive design iter-
ations continue to meet timing requirements.
XA devices are available in both the extended-temperature
Q-grade (-40
°
C to +125
°
C) and industrial I-grade (-40
°
C to
+100
°
C) and are qualified to the industry-recognized
AEC-Q100 standard.
The XA Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of conven-
tional ASICs. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement neces-
sary (impossible with ASICs).
•
•
•
Features
•
AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade
Table 1:
XA Spartan-IIE FPGA Family Members
Logic
Cells
1,728
2,700
3,888
5,292
6,912
Typical
System Gate Range
(Logic and RAM)
23,000 - 50,000
37,000 - 100,000
52,000 - 150,000
71,000 - 200,000
93,000 - 300,000
CLB
Array
(R x C)
16 x 24
20 x 30
24 x 36
28 x 42
32 x 48
Total
CLBs
384
600
864
1,176
1,536
Maximum
Available
User I/O
(1)
102
102
182
182
182
Maximum
Differential
I/O Pairs
83
86
114
120
120
Distributed
RAM Bits
24,576
38,400
55,296
75,264
98,304
Block
RAM Bits
32K
40K
48K
56K
64K
Device
XA2S50E
XA2S100E
XA2S150E
XA2S200E
XA2S300E
Notes:
1. User I/O counts include the four global clock/user input pins. See details in
Table 3, page 5
© 2002–2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering
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General Overview
The Spartan-IIE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. The XC2S400E has four col-
umns of block RAM. These functional elements are inter-
connected by a powerful hierarchy of versatile routing
channels (see
Figure 1).
Spartan-IIE FPGAs are customized by loading configura-
tion data into internal static memory cells. Unlimited repro-
gramming cycles are possible with this approach. Stored
values in these cells determine logic functions and intercon-
nections implemented in the FPGA. Configuration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes.
Spartan-IIE FPGAs are typically used in high-volume appli-
cations where the versatility of a fast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. Spartan-IIE FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-IIE
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DLL clock driv-
ers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
Spartan-IIE Family Compared to Spartan-II
Family
•
•
•
•
•
Higher density and more I/O
Higher performance
Unique pinouts in cost-effective packages
Differential signaling
- LVDS, Bus LVDS, LVPECL
V
CCINT
= 1.8V
- Lower power
- 5V tolerance with external resistor
- 3V tolerance directly
LVTTL and LVCMOS2 input buffers powered by V
CCO
instead of V
CCINT
Unique larger bitstream
•
•
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Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering
DLL
DLL
BLOCK RAM
BLOCK RAM
DLL
I/O LOGIC
DS077_01_052102
Figure 1:
Basic Spartan-IIE Family FPGA Block Diagram
DC Specifications
Absolute Maximum Ratings
(1)
Symbol
V
CCINT
V
CCO
V
REF
V
IN
V
TS
T
STG
T
J
Description
Supply voltage relative to GND
Supply voltage relative to GND
Input reference voltage
Input voltage relative to GND
(2,3)
Voltage applied to 3-state output
(3)
Storage temperature (ambient)
Junction temperature
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–65
-
Max
2.0
4.0
4.0
4.05
4.0
+150
+135
Units
V
V
V
V
V
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. V
IN
should not exceed V
CCO
by more than 3.6V over extended periods of time (e.g., longer than a day).
3. Maximum DC overshoot must be limited to either V
CCO
+ 0.5V or 10 mA, and undershoot must be limited to –0.5V or 10 mA,
whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to –2.0V or overshoot
to V
CCO
+ 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
4. For soldering guidelines, see the Packaging Information on the Xilinx Web site.
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BLOCK RAM
DLL
BLOCK RAM
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Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering
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Recommended Operating Conditions
Symbol
T
J
V
CCINT
V
CCO
T
IN
Description
Junction temperature
Supply voltage relative to GND
(1)
Supply voltage relative to GND
(2)
Input signal transition time
(3)
Min
–40
1.8 – 5%
1.2
-
Max
125
1.8 + 5%
3.6
250
Units
°C
V
V
ns
Notes:
1. Functional operation is guaranteed down to a minimum V
CCINT
of 1.62V (Nominal V
CCINT
–10%). For every 50 mV reduction in V
CCINT
below 1.71V (nominal V
CCINT
–5%), all delay parameters increase by 3%.
2. Minimum and maximum values for V
CCO
vary according to the I/O standard selected.
3. Input and output measurement threshold is ~50% of V
CCO
.
DC Characteristics Over Operating
Conditions
Symbol
Description
XA2S50E
XA2S100E
I
CCINTQ
Quiescent V
CCINT
supply current
(1)
XA2S150E
XA2S200E
XA2S300E
Notes:
1. With no output current loads, no active pull-up resistors, and all I/O pins 3-stated and floating.
Min
-
-
-
-
-
Max
200
350
450
550
650
Units
mA
mA
mA
mA
mA
Spartan-IIE Product Availability
Table 2
shows the package and speed grades available for
Spartan-IIE family devices.
Table 3
shows the maximum
Table 2:
Spartan-IIE Package and Speed Grade Availability
Pins
Type
Device
XA2S50E
XA2S100E
XA2S150E
XA2S200E
XA2S300E
Code
-6
-6
-6
-6
-6
144
Plastic TQFP
TQ144
I,Q
I,Q
-
-
-
I,Q
I,Q
I,Q
256
Fine Pitch
BGA
FT256
user I/Os available on the device and the number of user
I/Os available for each device/package combination.
Notes:
1. Q = –40°C to +125°C (T
J
)
2. I = –40°C to +100°C (T
J
)
4
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Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering
Table 3:
Spartan-IIE User I/O Chart
Available User I/O
According to Package Type
TQ144
102
102
-
-
-
FT256
-
-
182
182
182
Device
XA2S50E
XA2S100E
XA2S150E
XA2S200E
XA2S300E
Maximum User
I/O
102
102
182
182
182
Ordering Information
Example:
Device Type
Speed Grade
XA2S50E -6 TQ 144 Q
Temperature Range
Number of Pins
Package Type
Device Ordering Options
Device
XA2S50E
XA2S100E
XA2S150E
XA2S200E
XA2S300E
Speed Grade
-6 Standard Performance
Package Type / Number of Pins
TQ144 144-pin Plastic Thin QFP
FT256
256-ball Fine Pitch BGA
Temperature Range (T
J
)
Q = Automotive
Extended
I = Automotive
Industrial
–40°C to +125°C
–40°C to +100°C
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Product Specification
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