2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst
counter if burst is desired.
Pin arrangement for TQFP
A6
A7
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/
LD
A18
A8
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
V
SS
V
SS
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
1&
3/11/02;
v.1.8H
Alliance Semiconductor
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A11
A12
A13
A14
A15
A16
A17
* Pins 24 and 74 are NC in x16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
V
DD
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
TQFP 14 × 20mm*
2 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Functional description
The AS7C33512NTD16A/18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as
524,288 words × 16 or 18 bits and incorporates a LATE LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced write operation that
improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the
device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
NTD
™
devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle pipeline (flowthrough)
read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD
™
, write and
read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 16/18 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs (refer to
synchronous truth table on page 4.) In pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV/LD (burst advance) input to perform burst read, write and deselect operations. When ADV/LD is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device
operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD16A and AS7C33512NTD18A operate with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a sepa-
rate power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP and a 119-ball
14×20 mm BGA package.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
Address and control pins
I/O pins
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
5
7
Unit
pF
pF
Burst Order
Interleaved Burst Order
Starting Address
First increment
Second increment
Third increment
00
01
10
11
LBO=1
01
10
00
11
11
00
10
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order
00
01
10
11
LBO=0
01
10
10
11
11
00
00
01
11
00
01
10
3/11/02;
v.1.8H
Alliance Semiconductor
3 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b]
CE0, CE1,
CE2
ADV/LD
I/O Properties
I
I
I
I/O
I
CLOCK
SYNC
SYNC
SYNC
SYNC
Description
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted HIGH, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is HIGH.
Advance or Load. When sampled HIGH, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When LOW, a new
address is loaded.
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is HIGH.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This input should be static when the
device is in operation.
Flow-through mode.When low, enables single register flow-through mode. Connect to V
DD
if unused or for pipelined operation.
Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.
No connects. Note that pin 84 will be used for future address expansion to 18Mb density.
I
SYNC
R/W
BW[a,b]
OE
LBO
I
I
I
I
SYNC
SYNC
ASYNC
STATIC
FT
ZZ
NC
I
I
-
STATIC
ASYNC
-
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.5
–0.5
–0.5
–
–
–65
–65
Max
+4.6
V
DD
+ 0.5
V
DDQ
+ 0.5
1.8
50
+150
+135
Unit
V
V
V
W
mA
°
C
°
C
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
3/11/02;
v.1.8H
Alliance Semiconductor
4 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Synchronous truth table
CE0
H
X
X
L
L
X
X
CE1
X
L
X
H
H
X
X
CE2
X
X
H
L
L
X
X
ADV/LD
L
L
L
L
L
H
X
R/W
X
X
X
H
L
X
X
BW[a,b]
X
X
X
X
L
X
1
X
OE
X
X
X
X
X
X
X
CEN
L
L
L
L
L
L
H
Address source
NA
NA
NA
External
External
Burst counter
Stall
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect, high-Z
Deselect, high-Z
Deselect, high-Z
Begin read
Begin write
Burst
2
Inhibit the CLK
1
Should be low for Burst write, unless a specific byte/s need/s to be inhibited
2 Refer to state diagram below.
Key: X = Don’t Care, L = Low, H = High.
State Diagram for NTD SRAM
Burst
Read
Read
Read
Burst
Read
Dsel
Burst
Dse
l
Rea
d
Dsel
Dsel
Burst
ad
Re
W
rit
e
Read
Write
Write
Write
Write
ite
Wr
Burst
l
Dse
Burst
Write
Dsel
Burst
Recommended operating conditions
Parameter
Supply voltage
3.3V I/O supply
voltage
2.5V I/O supply
voltage
Address and
control pins
I/O pins
Ambient operating temperature
Symbol
V
DD
V
SS
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
IH
V
IL
V
IH
V
IL
T
A
Min
3.135
0.0
3.135
0.0
2.35
0.0
2.0
–0.5
2
2.0
–0.5
2
0
Nominal
3.3
0.0
3.3
0.0
2.5
0.0
–
–
–
–
–
Max
3.6
0.0
3.6
0.0
2.65
0.0
V
DD
+ 0.3
0.8
V
DDQ
+ 0.3
0.8
70
Unit
V
V
V
V
V
°
C
Input voltages
1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
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