ADVANCE
INFORMATION
CY26049-5
FailSafe™ PacketClock™
Global Communications Clock Generator
Features
• Fully integrated phase-locked loop (PLL)
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• 76.8-MHz output from 19.2-MHz input
• Low-jitter, high-accuracy outputs
• 3.3V ± 5% operation
• 16-lead TSSOP
Benefits
• Integrated high-performance PLL tailored for telecommuni-
cations frequency synthesis eliminates the need for external
loop filter components
• When reference is off, DCXO maintains clock outputs and
SAFE pin indicates FailSafe conditions
• DCXO maintains continuous operation should the input
reference clock fail
• Glitch-free transition simplifies system design
• Works with commonly available, low-cost 19.2-MHz crystal
• Zero-ppm error for all output frequencies
• Compatible across industry standard design platforms
• Industry standard package with 6.4 × 5.0 mm
2
footprint and
a height profile of just 1.1 mm
Logic Block Diagram
e xte rn a l p u lla b le c rysta l
(1 9 .2 M H z)
X IN
in p u t r e fe re n ce
(1 9 .2 M H z)
IC L K
F A IL S A F E
T M
CONTROL
D IG IT A L
C O N TR O LLE D
C R YSTAL
O S C IL L A T O R
PHASE
LO C K E D
LO O P
CLKA
7 6 .8 M H z
XOUT
O U TPU T
D IV ID E R
SA FE
IC L K d e te cte d
Cypress Semiconductor Corporation
Document #: 38-07485 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised September 8, 2003
ADVANCE
INFORMATION
Pin Configuration
CY26049-5
16-pin TSSOP
Top View
ICLK 1
NC 2
NC 3
NC 4
VDD 5
VSS 6
CLKA
7
16 NC
15 NC
14 NC
13 NC
12 VDD
11 VSS
10 SAFE
9 XOUT
CY26049-5
XIN 8
Pin Description
Pin Number Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ICLK
NC
NC
NC
VDD
VSS
CLKA
XIN
XOUT
SAFE
VSS
VDD
NC
NC
NC
NC
Reference Input Clock;
19.2 MHz.
No Connect.
No Connect.
No Connect.
Voltage Supply; 3.3V.
Ground.
Clock Output; 76.8 MHz.
Pullable Crystal Input;
19.2 MHz.
Pullable Crystal Output;
19.2 MHz.
High = reference ICLK within range, Low = reference ICLK out of range.
Ground.
Voltage Supply;
3.3V.
No Connect.
No Connect.
No Connect.
No Connect.
Pin Description
Selector Guide
Part Number
Input Frequency Range
Outputs
1
Output Frequencies
76.8 MHz
CY26049ZC-5 Reference Input Clock: 19.2 MHz
Crystal: 19.2-MHz pullable Crystal per Cypress Specification
Description
CY26049-5 is a FailSafe frequency synthesizer with a
reference clock input and 76.8-MHz output. The device
provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure. The continuous, glitch-free operation is achieved by
using a DCXO, which serves as a primary clock source. The
FailSafe control circuit synchronizes the DCXO oscillator with
the reference as long as the reference is within the pull range
of the crystal.
In the event of a reference clock failure the DCXO maintains
the last frequency of the reference clock. The unique feature
of the CY26049-5 is that the DCXO is in fact the primary
clocking source. When the reference clock is restored, the
DCXO automatically resynchronizes to the reference. The
status of the reference clock input, as detected by the
CY26049-5, is reported by the SAFE pin.
Document #: 38-07485 Rev. *A
Page 2 of 6
ADVANCE
INFORMATION
Absolute Maximum Conditions
Supply Voltage (V
DD
) ........................................–0.5 to +7.0V
DC Input Voltage........................................ –0.5V to V
DD
+0.5
Storage Temperature (Non-Condensing) .... –55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
CY26049-5
Data Retention @ Tj=125°C.................................. >10 Years
Package Power Dissipation....................................... 350mW
ESD (Human Body Model) MIL-STD-883.................... 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Recommended Pullable Crystal Specifications
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
DL
F
3SEPLI
F
3SEPLO
C
0
C
0
/C
1
C
1
Name
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance (ESR)
Ratio of third overtone mode ESR to
fundamental mode ESR
Crystal drive level
Fundamental mode
Ratio used because typical R
1
values
are much less than the maximum spec
No external series resistor assumed
Comments
Parallel resonance, fundamental mode,
AT cut
Min.
–
–
–
3
–
400
–
–
180
14.4
Typ.
19.2
14
–
–
0.5
–
–
–
–
18
Max.
–
–
25
–
2
–
–200
7
250
21.6
fF
mW
ppm
ppm
pF
Unit
MHz
pF
Ω
Third overtone separation from 3*F
NOM
High side
Third overtone separation from 3*F
NOM
Low side
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
Recommended Operating Conditions
Parameter
V
DD
T
AC
C
LOAD
t
pu
Operating Voltage
Ambient Temperature (Commercial Temperature)
Max Output Load Capacitance
Power-up time for all V
DD
’s to reach minimum specified
voltage (power ramps must be monotonic)
Description
Min.
3.15
0
–
0.05
Typ.
3.3
–
–
–
Max.
3.45
70
15
500
Unit
V
°C
pF
ms
DC Electrical Specifications
(Commercial Temp: 0°to 70°C)
Parameter
I
OH
I
OL
V
IH
V
IL
I
IH
I
IL
C
IN
I
DD
Description
Output High Current
Output Low Current
Input High Voltage
Input High Voltage
Input High Current
Input Low Current
Input Capacitance
Supply Current
C
LOAD
= 15 pF, V
DD
= 3.45V
Test Conditions
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
CMOS Levels
CMOS Levels
V
IH
=V
DD
V
IL
=0V
Min.
12
12
0.7
–
–
–
–
–
Typ.
24
24
–
–
5
5
–
–
Max.
–
–
–
0.3
10
10
7
45
Unit
mA
mA
V
DD
V
DD
µA
µA
pF
mA
AC Electrical Specifications
(Commercial Temp: 0° to 70° C)
Parameter
f
ICLK-E
LR
DC = t
2
/t
1
T
PJIT1
Description
Frequency, Input Clock
FailSafe Lock Range
[1]
Output Duty Cycle
Test Conditions
Input Clock Frequency, External Mode
Range of reference ICLK for Safe = High
Duty Cycle defined in
Figure 1,
measured at 50% of V
DD
RMS Period Jitter, RMS
Note:
1. Dependent on crystals chosen and crystal specs.
Min.
–
–250
45
–
–
Typ.
19.2
–
50
–
–
Max. Unit
–
55
250
50
MHz
%
ps
ps
+250 ppm
Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods
Document #: 38-07485 Rev. *A
Page 3 of 6
ADVANCE
INFORMATION
AC Electrical Specifications
(Commercial Temp: 0° to 70° C) (continued)
Parameter
t
6
t
fs_lock
f
error
ER
EF
Description
PLL Lock Time
FailSafe Lock Time
Frequency Synthesis Error
Rising Edge Rate
Falling Edge Rate
Test Conditions
Time for PLL to lock within ± 150 ppm of target frequency
Time for PLL to lock to ICLK (outputs phase aligned with
ICLK and Safe = High)
Actual mean frequency error vs. target
Output Clock Edge Rate, Measured from 20% to 80% of
V
DD
, C
LOAD
= 15 pF. See
Figure 2.
Output Clock Edge Rate, Measured from 20% to 80% of
V
DD
, C
LOAD
= 15 pF. See
Figure 2.
Min.
–
–
–
0.8
0.8
CY26049-5
Typ.
–
–
0
1.4
1.4
Max. Unit
3
7
–
2
2
ms
s
ppm
V/ns
V/ns
Voltage and Timing Definitions
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
80%
CLK
20%
t4
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Test Circuit
ICLK
1
2
3
4
16
15
14
13
VDD
5
12
VDD
0.1uF
6
11
10
9
0.1uF
CLKA
7
C
LOAD
8
19.2MHz
Ordering Information
Ordering Code
CY26049ZC-5
CY26049ZC-5T
Package Type
16-lead TSSOP
16-lead TSSOP—Tape and Reel
Operating Temperature Range
Commercial 0° to 70°C
Commercial 0° to 70°C
Document #: 38-07485 Rev. *A
Page 4 of 6
ADVANCE
INFORMATION
Package Drawing and Dimensions
16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
CY26049-5
51-85091-**
FailSafe and PacketClock are trademarks of Cypress Semiconductor. All product and company names mentioned in this
document are the trademarks of their respective holders.
Document #: 38-07485 Rev. *A
Page 5 of 6
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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