PRELIMINARY
CY28318
Spread Spectrum FTG for VIA Chipset
2CY28318
Features
• Single-chip system frequency synthesizer for VIA
SDRAM chipset
• Pin compatible with W144 and W211B
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog Timer for system recov-
ery
• Automatically switch to HW selected or SW pro-
grammed clock frequency when Watchdog Timer time-
outs
• Capable of generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for CPU, SDRAM and PCI
output clocks
• Programmable output skew between CPU, PCI and
SDRAM
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Available in 48-pin SSOP
Table 1. Mode Input Table
Mode
0
1
Pin 2
CPU_STOP#
REF0
Key Specifications
CPU to CPU Output Skew: ...........................................175 ps
PCI to PCI Output Skew: ..............................................500 ps
SDRAMIN to SDRAM0:12 Delay: ..................4.5 – 6.0 ns typ.
Table 2. Pin Selectable Frequency
Input Address
CPU_F, CPU1
FS3 FS2 FS1 FS0
(MHz)
1
1
1
1
133.6
1
1
1
0
75
1
1
0
1
100.2
1
1
0
0
66.8
1
0
1
1
79
1
0
1
0
110
1
0
0
1
115
1
0
0
0
120
0
1
1
1
133.3
0
1
1
0
83
0
1
0
1
100.0
0
1
0
0
66.6
0
0
1
1
122
0
0
1
0
129
0
0
0
1
138
0
0
0
0
95
PCI_F, 1:5
(MHz)
33.4
37.5
33.4
33.4
39.5
36.7
38.3
30
33.3
27.7
33.3
33.3
30.5
32.3
34.5
31.7
Block Diagram
VDD_REF
REF0/(CPU_STOP#)
X1
X2
XTAL
OSC
REF1/FS0
Pin Configuration
[1]
VDD_REF
REF0/(CPU_STOP#)*
GND_REF
X1
X2
VDD_PCI
PCI0/MODE*
PCI1/FS1*
GND_PCI
PCI2
PCI3
PCI4
PCI5
VDD_CORE
SDRAMIN
GND_SDRAM
SDRAM11
SDRAM10
VDD_SDRAM
SDRAM9
SDRAM8
GND_48MHz
SMBus SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_APIC
APIC
REF1/FS0*
GND_CPU
CPU_F
CPU1
VDD_CPU
RST#
SDRAM12
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDDRAM
SDRAM6
SDRAM7
VDD_48MHz
48MHz/FS2*
24_48MHz/FS3^
PLL Ref Freq
I/O Pin
Control
VDD-APIC
APIC
VDD_CPU
CPU_F
Stop
Clock
Control
÷2,3,4
CY28318
CPU1
PLL 1
VDD_PCI
PCI0/MODE
PCI1/FS1
PCI2
PCI3
PCI4
PCI5
RST#
VDD_48 MHz
48MHz/FS2
÷2
SDATA
SCLK
SMBus
Logic
PLL2
{
SDRAMIN
13
24_48MHz/FS3
VDD_SDRAM
SDRAM0:12
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.Pins marked with ^ are internal pull-down resis-
tors. Pins marked with * are internal pull-up resistors.
Cypress Semiconductor Corporation
Document #: 38-07272 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 27, 2001
PRELIMINARY
Pin Definitions
Pin Name
CPU_F
CPU1
PCI2:5
PCI1/FS1
Pin No.
44
43
10, 11, 12, 13
8
Pin Type
O
O
O
I/O
Pin Description
CY28318
Free-running CPU Clock:
Free-running CPU output clock. See
Table 2
and
Table 7
for detailed frequency information.
CPU Clock Output 1:
This CPU clock output is controlled by the CPU_STOP#
and control pin.
PCI Clock Outputs 2 through 5:
Frequency is set by FS0:3 inputs or through
serial input interface, see
Table 2
and
Table 7
for details.
Fixed PCI Clock Output/Frequency Select 1:
As an output, frequency is set
by FS0:3 inputs or through serial input interface. This pin also serves as a
power-on strap option to determine device operating frequency as described
in
Table 2
and
Table 7.
Fixed PCI Clock Output/Mode:
As an output, frequency is set by the FS0:3
inputs or through serial input interface, see
Table 2
and
Table 7.
This pin also
serves as a power-on strap option to determine the function of pin 2, see
Table
1
for details.
Reset# Output:
Open drain system reset output.
PCI0/MODE
7
I/O
RST#
41
I
(Open-
Drain)
O
I/O
APIC
48MHz/FS2
47
26
APIC Clock Output:
Provides 14.318-MHz fixed frequency.
48-MHz Output/Frequency Select 2:
48 MHz is provided in normal operation.
In standard PC systems, this output can be used as the reference for the
Universal Serial Bus host controller. This pin also serves as a power-on strap
option to determine device operating frequency as described in
Table 2
and
Table 7.
24_48-MHz Output/Frequency Select 3:
In standard PC systems, this output
can be used as the clock input for a Super I/O chip. The output frequency is
controlled by Configuration Byte 3 bit[6]. The default output frequency is
24 MHz. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 2
and
Table 7
Reference Clock Output 1/Frequency Select 2:
3.3V 14.318-MHz output
clock. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 2
and
Table 7.
Reference Clock Output 0 or CPU_STOP# Input Pin:
Function is determined
by the MODE pin. When CPU_STOP# input is asserted LOW, it will disable
CPU1 output and drive it to logic 0. When this pin is configured as an output,
this pin becomes a 3.3V 14.318-MHz output clock.
Buffered Input Pin:
The signal provided to this input pin is buffered to 13
outputs (SDRAM0:12).
Buffered Outputs:
These thirteen dedicated outputs provide copies of the
signal provided at the SDRAMIN input, and they are deactivated when
PWRDWN# input is set LOW.
Clock pin for SMBus circuitry.
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input:
This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
Crystal Connection:
An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
24_48MHz/
FS3
25
I/O
REF1/FS0
46
I/O
REF0/
CPU_STOP#
2
I/O
SDRAMIN
SDRAM0:12
15
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17, 40
24
23
4
I
O
SCLK
SDATA
X1
I
I/O
I
X2
5
O
Document #: 38-07272 Rev. **
Page 2 of 22
PRELIMINARY
Pin Definitions
(continued)
Pin Name
VDD_REF,
VDD_PCI,
VDD_CORE,
VDD_SDRAM,
VDD_48 MHz
VDD_CPU,
VDD_APIC
GND_REF,
GND_PCI,
GND_SDRAM,
GND_48MHz
GND_CPU
Pin No.
1, 6, 14, 19,
27, 30, 36
Pin Type
P
Pin Description
CY28318
Power Connection:
Power supply for core logic, PLL circuitry, SDRAM out-
puts, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output,
connect to 3.3V supply.
42, 48
3, 9, 16, 22,
33, 39, 45
P
G
Power Connection:
Connect to 2.5V supply
Ground Connections:
Connect all ground pins to the common system ground
plane.
Document #: 38-07272 Rev. **
Page 3 of 22
PRELIMINARY
Serial Data Interface
The CY28318 features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions.
Data Protocol
The clock driver serial protocol supports byte/word write,
byte/word read, block write and block read operations from the
Table 3. Command Code Definition
Bit
7
6:0
CY28318
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte with
the ability to stop after any complete byte has been trans-
ferred. For byte/word write and byte read operations, system
controller can access individual indexed byte. The offset of the
indexed byte is encoded in the command code.
The definition for the command code is defined in
Table 3.
Descriptions
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
Table 4. Block read and block write protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
...
...
...
...
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from slave
Data byte 0 - 8 bits
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data Byte N/Slave Acknowledge...
Data Byte N - 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
...
...
...
...
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Byte count from slave - 8 bits
Acknowledge
Data byte from slave - 8 bits
Acknowledge
Data byte from slave - 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave - 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
Document #: 38-07272 Rev. **
Page 4 of 22
PRELIMINARY
Table 5. Word Read and Word Write Protocol
Word Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
Acknowledge from slave
Data byte low- 8 bits
Acknowledge from slave
Data byte high - 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address - 7 bits
Write
Acknowledge from slave
Word Read Protocol
Description
CY28318
Command Code - 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data byte low from slave - 8 bits
Acknowledge
Data byte high from slave - 8 bits
NOT acknowledge
Stop
19
20:27
28
29:36
37
38
19
20
21:27
28
29
30:37
38
39:46
47
48
Table 6. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
Acknowledge from slave
Data byte - 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data byte from slave - 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Document #: 38-07272 Rev. **
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