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ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter
May 28, 2009
ADC08D1520QML
Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D
Converter
General Description
The ADC08D1520 is an 8–Bit, dual channel, low power, high
performance CMOS analog-to-digital converter that builds
upon the ADC08D1000 platform. The ADC08D1520 digitizes
signals to 8 bits of resolution at sample rates up to 1.7 GSPS.
It has expanded features compared to the ADC08D1000,
which include a test pattern output for system debug, clock
phase adjust, and selectable output demultiplexer modes.
Consuming a typical 2.0W in Demultiplex Mode at 1.5 GSPS
from a single 1.9 Volt supply, this device is guaranteed to have
no missing codes over the full operating temperature range.
The unique folding and interpolating architecture, the fully dif-
ferential comparator design, the innovative design of the in-
ternal sample-and-hold amplifier and the self-calibration
scheme enable a very flat response of all dynamic parameters
beyond Nyquist, producing a high 7.2 Effective Number of Bits
(ENOB) with a 748 MHz input signal and a 1.5 GHz sample
rate while providing a 10
-18
Code Error Rate (C.E.R.) Output
formatting is offset binary and the Low Voltage Differential
Signaling (LVDS) digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable common
mode voltage between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 Demultiplexed Mode is se-
lected, the output data rate is reduced to half the input sample
rate on each bus. When Non-Demultiplexed Mode is select-
ed, that output data rate on channels DI and DQ are at the
same rate as the input sample clock. The two converters can
be interleaved and used as a single 3 GSPS ADC.
The converter typically consumes less than 2.9 mW in the
Power Down Mode and is available in a 128-pin, thermally
enhanced, multi-layer ceramic quad package and operates
over the Military (-55°C
≤
T
A
≤
+125°C) temperature range.
Features
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Total Ionizing Dose
300 krad(Si)
Single Event Latch-up
120 MeV-cm
2
/mg
Single +1.9V ±0.1V Operation
Interleave Mode for 2x Sample Rate
Multiple ADC Synchronization Capability
Adjustment of Input Full-Scale Range, Offset and Clock
Phase Adjustment
Choice of SDR or DDR output clocking
1:1 or 1:2 Selectable Output Demux
Second DCLK output
Duty Cycle Corrected Sample Clock
Test pattern
Serial Interface for Extended Control
Key Specifications
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Resolution
Max Conversion Rate
Code Error Rate
ENOB @ 748 MHz Input
DNL
Power Consumption
—
Operating in 1:2 Demux Output
—
Power Down Mode
8 Bits
1.5 GSPS (min)
10
-18
(typ)
7.2 Bits (typ)
±0.15 LSB (typ)
2.0 W (typ)
2.9 mW (typ)
Applications
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Direct RF Down Conversion
Digital Oscilloscopes
Communications Systems
Test Instrumentation
Ordering Information
NS Part Number
ADC08D1520WG-QV
ADC08D1520WGFQV
SMD Part Number
5962–0721401VZC
5962F0721401VZC
300 krad(Si)
NS Package Number
EM128A
EM128A
Package Discription
128L, CERQUAD
GULLWING
128L, CERQUAD
GULLWING
© 2009 National Semiconductor Corporation
300247
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ADC08D1520QML
Block Diagram
30024753
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ADC08D1520QML
Pin Configuration
30024701
Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance.
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ADC08D1520QML
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude
and reduced power consumption. See
1.1.6 The LVDS
Outputs.
When the extended control mode is enabled, this
pin functions as the SCLK input which clocks in the serial
data. See
1.2 NON-EXTENDED CONTROL/EXTENDED
CONTROL
for details on the extended control mode. See
1.3 THE SERIAL INTERFACE
for description of the serial
interface.
A logic high on the PDQ pin puts only the Q-Channel ADC
into the Power Down mode.
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. See
1.1.5.2 OutEdge and
Demultiplex Control Setting
When this pin is connected to
1/2 the supply voltage,V
A
/2, DDR clocking is enabled. When
the Extended Control Mode is enabled, this pin functions as
the SDATA input. See
1.2 NON-EXTENDED CONTROL/
EXTENDED CONTROL
for details on the Extended Control
Mode. See
1.3 THE SERIAL INTERFACE
for description of
the serial interface.
DCLK Reset. When single-ended DCLK_RST is selected by
setting pin 52 logic high or to V
A
/2, a positive pulse on this
pin is used to reset and synchronize the DCLK outputs of
multiple converters. See
1.5 MULTIPLE ADC
SYNCHRONIZATION
for detailed description. When
differential DCLK_RST is selected by setting pin 52 logic low,
this pin receives the positive polarity of a differential pulse
signal used to reset and synchronize the DCLK outputs of
multiple converters.
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode.
Calibration Cycle Initiate. A minimum t
CAL_L
input clock
cycles logic low followed by a minimum of t
CAL_H
input clock
cycles high on this pin initiates the calibration sequence. See
2.5.2 Calibration
for an overview of calibration and
2.5.2.1
Initiating Calibration
for a description of calibration.
Full Scale Range Select, Alternate Extended Control Enable
and DCLK_RST-. This pin has two functions. It can
conditionally control the ADC full-scale voltage, or become
the negative polarity signal of a differential pair in differential
DCLK_RST Mode. If pin 52 and pin 41 are connected at logic
high, this pin can be used to set the full-scale-range. When
used as the FSR pin, a logic low on this pin sets the full-scale
differential input range to a reduced V
IN
input level. A logic
high on this pin sets the full-scale differential input range to
Higher V
IN
input level. See Converter Electrical
Characteristics. When pin 52 is held at logic low, this pin acts
as the DCLK_RST- pin. When in differential DCLK_RST
Mode, there is no pin-controlled FSR and the full-scale-range
is defaulted to the higher V
IN
input level.
3
OutV / SCLK
29
PDQ
4
OutEdge / DDR /
SDATA
15
DCLK_RST/
DCLK_RST+
26
PD
30
CAL
14
FSR/DCLK_RST-
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