The UT54ACS138E is a 3-line to 8-line decoder/demultiplexer
designed to be used in high-performance memory-decoding or
data-routing applications requiring very short propagation delay
times.
The conditions at the binary select inputs and the three enable
inputs select one of eight output lines. Two active-low and one
active-high enable inputs reduce the need for external gates of
inverters when expanding. A 24-line decoder can be implement-
ed without external inverters and a 32-line decoder requires only
one inverter. An enable input can be used as a data input for
demultiplexing applications.
The device is characterized over full military temperature range
of -55C to +125C.
FUNCTION TABLE
ENABLE INPUTS
G1
X
L
X
H
H
H
H
H
H
H
H
G2A
X
X
H
L
L
L
L
L
L
L
L
G2B
H
X
X
L
L
L
L
L
L
L
L
C
X
X
X
L
L
L
L
H
H
H
H
SELECT INPUTS
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
Y0
H
H
H
L
H
H
H
H
H
H
H
PINOUT
16-Lead Flatpack
Top View
A
B
C
G2A
G2B
G1
Y7
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
OUTPUT
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
1
LOGIC SYMBOL
A
(1)
BIN/OCT
1
2
4
0
1
2
3
4
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(7)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G2B
G1
G2A
A
B
C
(1)
(2)
(3)
DMUX
1
2
4
B (2)
(3)
C
0
G
---
7
0
1
2
3
4
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(7)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G1
G2A
G2B
(6)
(4)
(5)
&
EN
5
6
7
(6)
(4)
(5)
&
EN
5
6
7
Note:
1. Logic symbols in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM
(15)
(14)
G1
ENABLE
(6)
Y0
Y1
G2A (4)
G2B (5)
(13) Y2
(12)
(11)
(10)
Y3
DATA
Y4
Y5
Y6
Y7
A
SELECT
B
(1)
(2)
(9)
(7)
C (3)
2
3
EN
A
B
C
EN
A
B
C
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H
A
B
C
EN
A
B
C
EN
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Y0 Y2
Y
31
Expansion to 1-of-32 Decoding
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
108
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
JC
I
I
P
D2
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation permitted @ Tc=125
o
C
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
15.0
10
3.3
UNITS
V
V
C
C
C
C/W
mA
W
Note:
1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, P
D
= (T
j(max)
- T
c(max)
) /
jc
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
C
4
DC ELECTRICAL CHARACTERISTICS
(Pre and Post-Radiation)*
(V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
, -55C < T
C
< +125C)
;
Unless otherwise noted, Tc is per the temperature range ordered
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