2.5V LVDS, 1:16 Glitchless Clock
Buffer TERABUFFER™ II
General Description
The IDT5T93GL16 2.5V differential clock buffer is a user-selectable
differential input to sixteen LVDS outputs. The fanout from a
differential input to sixteen LVDS outputs reduces loading on the
preceding driver and provides an efficient clock distribution network.
The IDT5T93GL16 can act as a translator from a differential HSTL,
eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be
used to translate to LVDS outputs. The redundant input capability
allows for a glitchless change-over from a primary clock source to a
secondary clock source. Selectable inputs are controlled by SEL.
During the switchover, the output will disable low for up to three clock
cycles of the previously-selected input clock. The outputs will remain
low for up to three clock cycles of the newly-selected clock, after
which the outputs will start from the newly-selected input. A FSEL
pin has been implemented to control the switchover in cases where
a clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T93GL16 outputs can be asynchronously
enabled/disabled. When disabled, the outputs will drive to the value
selected by the GL pin. Multiple power and grounds reduce noise.
IDT5T93GL16
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
DATA SHEET
Features
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Guaranteed low skew: <25ps (maximum)
Very low duty cycle distortion: <100ps (maximum)
High speed propagation delay: <2ns (maximum)
Up to 650MHz operation
Glitchless input clock switching
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interfaces
Selectable differential inputs to sixteen LVDS outputs
Power-down mode
At power-up, FSEL should be LOW
2.5V V
DD
-40°C to 85°C ambient operating temperature
Available in VFQFPN package
Recommends IDT5T9316 if glitchless input selection is not
required
For functional replacement use 8530I-01
Pin Assignment
Q16
Q13
V
DD
FSEL
SEL
Q16
Q15
Q14
Q15
Q14
Q13
V
DD
PD
Applications
•
Clock distribution
G1
V
DD
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
V
DD
A1
A1
1
2
3
4
5
6
7
8
9
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
G2
V
DD
Q12
Q12
Q11
Q11
Q10
Q10
Q9
Q9
V
DD
A2
A2
10
11
28
12
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
Q6
Q7
Q7
Q8
Q8
V
DD
GND
nc
V
DD
GL
Q5
Q5
Q6
IDT5T93GL16
52-Lead VFQFPN
K package
Top View
IDT5T93GL16 REVISION B MARCH 12, 2014
1
© 2014 Integrated Device Technology, Inc.
IDT5T93GL16 Data Sheet
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Block Diagram
GL
G1
OUTPUT
CONTROL
Q1
Q1
OUTPUT
CONTROL
Q2
Q2
PD
OUTPUT
CONTROL
Q3
Q3
OUTPUT
CONTROL
Q4
Q4
OUTPUT
CONTROL
A1
A1
Q5
Q5
1
OUTPUT
CONTROL
Q6
Q6
A2
A2
0
OUTPUT
CONTROL
Q7
Q7
SEL
FSEL
G2
OUTPUT
CONTROL
Q8
Q8
OUTPUT
CONTROL
Q9
Q9
OUTPUT
CONTROL
Q10
Q10
OUTPUT
CONTROL
Q11
Q11
OUTPUT
CONTROL
Q12
Q12
OUTPUT
CONTROL
Q13
Q13
OUTPUT
CONTROL
Q14
Q14
OUTPUT
CONTROL
Q15
Q15
OUTPUT
CONTROL
Q16
Q16
IDT5T93GL16 REVISION B MARCH 12, 2014
2
© 2014 Integrated Device Technology, Inc.
IDT5T93GL16 Data Sheet
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Table 1. Pin Descriptions
Name
A[1:2]
Input
Type
Adjustable
(1, 4)
Description
Clock input. A
[1:2]
is the "true" side of the differential clock input.
Complementary clock inputs. A[1:2] is the complementary side of A[1:2]
.
For LVTTL single-ended operation, A[1:2] should be set to the desired toggle voltage for
A[1:2]:
3.3V LVTTL V
REF
= 1650mV
2.5V LVTTL V
REF
= 1250mV
Gate control for differential outputs Q1 and Q1 through Q8 and Q8. When G1 is LOW, the
differential outputs are active. When G1 is HIGH, the differential outputs are asynchronously
driven to the level designated by GL
(2)
.
Gate control for differential outputs Q9 and Q9 through Q16 and Q16. When G2 is LOW, the
differential outputs are active. When G2 is HIGH, the differential outputs are asynchronously
driven to the level designated by GL
(2)
.
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary"
outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs
disable HIGH.
Clock outputs.
Complementary clock outputs.
Reference clock select. When LOW, selects A2 and A2.
When HIGH, selects A1 and A1.
Power-down control. Shuts off entire chip. If LOW, the device goes into LOW power mode.
Inputs and outputs are disabled. Both "true" and "complementary" outputs will pull to V
DD
. Set
HIGH for normal operation.
(3)
At a rising edge, FSEL forces select to the input designated by SEL. Set LOW for normal
operation. At power-up, FSEL should be LOW.
Power supply for the device core and inputs.
Ground.
A[1:2]
Input
Adjustable
(1, 4)
G1
Input
LVTTL
G2
Input
LVTTL
GL
Q[1:16]
Q[1:16]
SEL
Input
Output
Output
Input
LVTTL
LVDS
LVDS
LVTTL
PD
Input
LVTTL
FSEL
V
DD
GND
Input
LVTTL
Power
Power
NOTES:
1.
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2.
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
3.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
4.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
IDT5T93GL16 REVISION B MARCH 12, 2014
3
© 2014 Integrated Device Technology, Inc.
IDT5T93GL16 Data Sheet
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Table 2. Pin Characteristics
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
Maximum
3
Units
pF
NOTE: This parameter is measured at characterization but not tested.
Function Tables
Table 3A. Gate Control Output Table
Control Outputs
GL
0
0
1
1
G
0
1
0
1
Q[1:16]
Toggling
LOW
Toggling
HIGH
Outputs
Q[1:16]
Toggling
HIGH
Toggling
LOW
Table 3B. Input Selection Table
Selection SEL pin
0
1
Inputs
A2/A2
A1/A1
IDT5T93GL16 REVISION B MARCH 12, 2014
4
© 2014 Integrated Device Technology, Inc.
IDT5T93GL16 Data Sheet
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Power Supply Voltage, V
DD
Input Voltage, V
I
Output Voltage, V
O
Not to exceed 3.6V
Storage Temperature, T
STG
Junction Temperature, T
J
Rating
-0.5V to +3.6V
-0.5V to +3.6V
-0.5 to V
DD
+0.5V
-65C to +150C
150C
Recommended Operating Range
Symbol
T
A
V
DD
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Minimum
-40
2.3
Typical
+25
2.5
Maximum
+85
2.7
Units
C
V
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics
(1)
,
T
A
= -40°C to 85°C
Symbol
I
DDQ
I
TOT
I
PD
Parameter
Quiescent V
DD
Power Supply Current
Total Power
V
DD
Supply Current
Total Power Down
Supply Current
Test Conditions
V
DD
= Max.,
All Input Clocks = LOW
(2)
; Outputs enabled
V
DD
= 2.7V;
F
REFERENCE
Clock = 650MHz
PD = LOW
Minimum
Typical
(2)
Maximum
350
360
5
Units
mA
mA
mA
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
NOTE 2: The true input is held LOW and the complementary input is held HIGH.
IDT5T93GL16 REVISION B MARCH 12, 2014
5
© 2014 Integrated Device Technology, Inc.
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