The outputs of the UT7R995 can be configured to run at fre-
quencies ranging from 6 MHz to 200 MHz. Each output bank
has the ability to run at separate frequencies and with various
phase skew. Depending upon the output used for feedback to
the PLL, numerous clock division and multiplication options
exist.
The following discussion and list of tables will summarize the
available configuration options for the UT7R995. Tables 1
through 11, are relevant to the following configuration discus-
sions.
Table 1. Feedback Divider Settings (N-factor)
Table 2. Reference Divider Settings (R-Factor)
Table 3. Output Divider Settings - Bank 3 (K-factor)
Table 4. Output Divider Settings - Bank 4 (M-Factor)
Table 5. Frequency Divider Summary
Table 6. Calculating Output Frequency Settings
Table 7. Frequency Range Select
Table 8. Multiplication Factor (MF) Calculation
Table 9. Output Skew Settings
Table 10: Signal Propagation Delays in Various Media
Table 11. PE/HD Settings
Table 12. Power Supply Constraints
1.1 Divider Configuration Settings:
The feedback input divider is controlled by the 3-level DS[1:0]
pins as indicated in Table 1 and the reference input divider is
controlled by the 3-level PD/DIV pin as indicated in Table 2.
Although the Reference divider will continue to operate when
the UT7R995 is in the standard TEST mode of operation, the
Feedback Divider will not be available.
Table 1: Feedback Divider Settings (N-factor)
DS[1:0]
LL
LM
LH
ML
MM
MH
HL
HM
HH
Table 2: Reference Divider Settings (R-factor)
PD/DIV
LOW
1
MID
HIGH
Operating Mode
Powered Down
Normal Operation
Normal Operation
Reference Input
Divider -
(R)
Not Applicable
2
1
Note: 1.
When PD/DIV = LOW, the device enters power-down mode.
In addition to the reference and feedback dividers, the
UT7R995 includes output dividers on Bank 3 and Bank 4,
which are controlled by 3F[1:0] and 4F[1:0] as indicated in Ta-
bles 3 and 4, respectively.
Table 3: Output Divider Settings - Bank 3 (K-factor)
3F(1:0)
LL
HH
Bank 3 Output Divider -
(K)
2
4
Note: 1.
These states are used to program the phase of the respective banks.
Please see Equation 1 along with Tables 8 and 9.
PM
4F[1:0]
LL
Other
1
Table 4: Output Divider Settings - Bank 4 (M-factor)
Bank 4 Output Divider
(M)
2
1
2
3
4
5
1
EV
Feedback Input
Divider -
(N)
Permitted Output
Divider (K or M)
Connected to FB
1 or 2
1
EL
O
Note: 1.These
states are used to program the phase of the respective banks.
Please see Equation 1 along with Tables 8 and 9.
Each of the four divider options and their respective settings are
summarized in Table 5. By applying the divider options in Ta-
ble 5 to the calculations shown in Table 6, the user determines
the proper clock frequency for every output bank.
Table 5: Frequency Divider Summary
Division
Factors
N
R
K
M
D
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
1
1
IN
6
EN
T
Other
1
1
Available Divider Settings
1, 2, 3, 4, 5, 6, 8, 10, 12
1, 2
1, 2, 4
1, 2
8
10
12
3
Table 6: Calculating Output Frequency Settings
Configuration
Clock Output
Connected to FB
1Qn or 2Qn
3Qn
4Qn
Output Frequency
1Q[1:0]
1
and
2Q[1:0]
1
(N/R) * f
XTAL
(N/R) * K * f
XTAL
(N/R) * M * f
XTAL
(N/R) * (1/K) * f
XTAL
(N/R) * f
XTAL
(N/R) * (M/K) * f
XTAL
(N/R) * (1/M) * f
XTAL
(N/R) * (K/M) * f
XTAL
(N/R) * f
XTAL
3Q[1:0]
4Q[1:0]
Notes:
1. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the nominal VCO operating frequency (f
NOM
)
at a given reference frequency (f
XTAL
) and the divider and feedback configuration. The user must select a configuration and a reference frequency that will generate
a VCO frequency that is within the range specified by FS pin. Please see Table 7.
1.2 Frequency Range and Skew Selection:
The PLL in the UT7R995 operates within three nominal fre-
quency ranges. Each of which is selectable by the user through
the 3-level FS control pin. The selected FS settings given in Ta-
ble 7 determine the nominal operating frequency range of the
divide-by-one outputs of the UT7R995. Reference the first col-
umn of equation in Table 6 to calculate the value of f
NOM
for
any given feedback clock.
Table 7: Frequency Range Select
FS
L
M
H
Selectable output skew is in discrete increments of time unit
(t
U
). The value of t
U
is determined by the FS setting and the
maximum nominal frequency. The equation to be used to deter-
mine the t
U
value is as follows:
T
t
u
Equation 1.
=
1
(f
NOM
* MF)
Nominal PLL Frequency Range
(f
NOM
)
24 to 50 MHz
48 to 100MHz
96 to 200 MHz
IN
D
EV
4
EL
O
PM
The f
NOM
term, selected by the FS signal, is found in Table 7,
and the multiplication factor (MF), also determined by FS, is
shown in Table 8.
After calculating the time unit (t
U
) based on the nominal PLL
frequency (f
NOM
) and multiplication factor (MF), the circuit
designer plans routing requirements of each clock output and its
respective destination receiver. With an understanding of signal
propagation delays through a conductive medium (see Table
10), the designer specifies trace lengths which ensure a signal
propagation delay that is equal to one of the t
U
multiples show
in Table 9. For each output bank, the t
U
skew factors are select-
ed with the tri-level, bank-specific, nF[1:0] pins.
EN
Table 8: MF Calculation
FS
L
M
H
MF
32
16
8
f
NOM
at which t
U
is 1.0ns
31.25 MHz
62.5 MHz
125 MHz
Table 10: Examples of Common Signal Propagation Delays
found in Various Mediums
Medium
Air (Radio Waves)
Coax. Cable (75% Velocity)
Coax. Cable (66% Velocity)
Propagation
Dielectric
Delay (ps/inch) Constant
85
113
129
140 - 180
180
240 - 270
1.0
1.8
2.3
2.8 - 4.5
4.5
8 - 10
Table 9: Output Skew Settings
nF[1:0]
LL
1, 2
FR4 PCB, Outer Trace
Skew
1Q[1:0], 2Q[1:0]
-4t
U
-3t
U
-2t
U
-1t
U
Zero Skew
+1t
U
+2t
U
+3t
U
+4t
U
Skew
3Q[1:0]
Divide by 2
-6t
U
-4t
U
-2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Divide by 4
Skew
4Q[1:0]
Divide by 2
-6t
U
-4t
U
-2t
U
Zero Skew
FR4 PCB, Inner Trace
Alumina PCB, Inner Trace
LM
LH
ML
MM
MH
HL
HM
HH
2
+4t
U
+6t
U
Inverted
3
IN
D
EV
EL
5
O
Notes:
1. nF[1:0] = LL disables bank specific outputs if TEST=MID and sOE = HIGH.
2. When TEST=MID or HIGH, the Divide-by-2, Divide-by-4, and Inversion
options function as defined in Table 9.
3. When 4Q[1:0] are set to run inverted (4F[1:0] = HH), sOE disables these out-
puts HIGH when PE/HD = HIGH or MID, sOE disables them LOW when
1 Introduction
In the mid-1960s, American scientist Maas conducted extensive experimental research on the charging process of open-cell batteries and proposed an acceptable charging curve for ...[详细]
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