Microcomputer Components
Technical Support Group Munich
HL MCB AT 1
Errata Sheet
February 2, 1996 / Release 1.1
Device :
Stepping Code / Marking :
SAB-C167-LM,
SAF-C167-LM
ES-BB, BC
This errata sheet describes the functional problems known in this step. Problem
classification and numbering is performed relative to modules. For backward
reference, a table which lists the problems of previous steps has been included.
The C167-LM devices are mounted in a 144-pin Plastic Metric Quad Flat Pack
(P-MQFP-144-1) package.
Note:
devices which are marked as
ES-BB
are engineering samples which may
not be completely tested in all functional and electrical characteristics. They
should be used for functional evaluation only.
Changes
from Errata Sheet
Rel. 1.0
to this Errata Sheet
Rel. 1.1:
-
CC31/ADC Interference (ADC.8)
Errata Sheet C167-LM, ES-BB, BC, 1.1
-1/7-
Functional Problems
The following malfunctions are known in this step:
ADC.8:
CC31/ADC Interference
When the channel injection option is
not
enabled for the A/D converter (i.e. bit
ADCIN = 0 and ADWR = 0), and a capture or compare event is generated by
channel CC31 of the CAPCOM2 unit, the current A/D conversion (if in progress)
will be completed, but no further A/D conversion can be performed (i.e. the A/D
converter is blocked). The same problem will occur when bit ADCRQ is set to '1'
by software and channel injection is not enabled.
Note:
Pin CC31IO/P7.7 may be used for general purpose I/O without affecting
operation of the A/D converter.
Workaround 1:
Use other CAPCOM channels than CC31 for capture or compare functions.
Workaround 2:
Allow a (dummy) channel injection to be triggered by the capture/compare event
on CC31. After the injected conversion is finished, register ADDAT2 must be
read.
CPU.8 :
Jump instructions in EXTEND sequence
When a jump or call is taken in an EXTS, EXTSR, EXTP, or EXTPR sequence, a
following data access included in the EXTEND sequence might be performed to a
wrong segment or page number.
Note:
ATOMIC or EXTR sequences are
not
affected by this problem.
Example: Accessing double-word data with a check on segment overflow
between the two accesses (R5 contains 8-bit segment number, R4 contains
16-bit intra-segment offset address):
EXTS R5,#4
; start EXTEND sequence
MOV R10,[R4+] ; get first word
CMP R4,#0
; check for segment overflow
JMPR cc_NZ,Next ; jump if no segment overflow
ADD R5,#1
; increment to next segment
EXTS R5,#1
; continue EXTEND sequence
Next: MOV R11,[R4]
; get second word
With this sequence, the problem can occur when the jump is taken to label Next;
the data access here might use a wrong segment number.
Errata Sheet C167-LM, ES-BB, BC, 1.1
-2/7-
Workaround:
Do not use jumps or calls in EXTS, EXTSR, EXTP, or EXTPR sequences. This
can be done very easily since only an actual data access must be included in an
EXTEND sequence. All other instructions, such as comparisons and jumps, do
not necessarily have to be in the EXTEND sequence.
For the example shown above, there are several possibilities to get around the
problem:
a) with a jump, but EXTEND sequence only for the data accesses
EXTS R5,#1
MOV R10,[R4+]
CMP R4,#0
JMPR cc_NZ,Next
ADD R5,#1
Next: EXTS R5,#1
MOV R11,[R4]
b) without a jump
EXTS R5,#4
MOV R10,[R4]
ADD R4,#2
ADDC R5,#0
EXTS R5,#1
MOV R11,[R4]
; EXTEND sequence
; get first word
; increment pointer here
; add possible overflow from pointer inc.
; continue EXTEND sequence
; get second word
; EXTEND sequence only for data access
; get first word
; check for segment overflow
; jump if no segment overflow
; increment to next segment
; second EXTEND sequence for data access
; get second word
The first EXTEND instruction of example b) can also be modified such that only
the following data access is included in the EXTEND sequence (EXTS R5,#1).
This additionally has the effect of a reduced interrupt latency.
Notes on Compilers and Operating Systems
Such critical sequences might be produced within library functions of C-Compilers
when accessing huge double-word data, or in operating systems. We are in close
contact with the compiler and operating system manufacturers in order to
determine eventual problems and workarounds. Information on possible updates
will be published as soon as available. Please contact your tool manufacturer or
the Siemens Microcontroller Mailbox (Tel. 0049-(0)89-49 84 31). From the
following compiler versions, we currently know that they are
not
affected by this
problem:
BSO/Tasking V4.0r3
HighTec C16x-GNU-C V3.1
Keil C166 V2.60
Errata Sheet C167-LM, ES-BB, BC, 1.1
-3/7-
CPU.9:
PEC Transfers during instruction execution from Internal RAM
When a PEC transfer occurs after a jump with cache hit during instruction
execution from internal RAM (locations 0F600h - 0FDFFh), the instruction
following the jump target instruction may not be (correctly) executed. This
problem occurs when the following sequence of conditions is true:
i) a loop terminated with a jump which can load the jump target cache (possible
for JMPR, JMPA, JB, JNB, JBC, JNBS) is executed in the internal RAM
ii) at least two loop iterations are performed, and no JMPS, CALLS, RETS, TRAP,
RETI instruction or interrupt is processed between the last and the current
iteration through the loop (i.e. the condition for a jump cache hit is true)
iii) a PEC transfer is performed after the jump at the end of the loop has been
executed
iv) the jump target instruction is a double word instruction
Note: No problem
will occur during instruction execution from the internal
XRAM
(locations 0E000h - 0E7FFh).
Workaround 1:
Place a single word instruction (e.g. NOP) at the jump target address in the
internal RAM.
Workaround 2:
Use JMPS (unconditional) or JMPI (conditional) instructions at the end of the loop
in the internal RAM. These instructions will not use the jump cache.
CPU.11:
Stack Underflow Trap during Restart of interrupted Multiply
Wrong multiply results may be generated when a STUTRAP (stack underflow) is
caused by the last implicit stack access (= pop PSW) of a RETI instruction which
restarts an interrupted MUL/MULU instruction.
No problem will occur in systems where the stack overflow/underflow detection is
not used, or where an overflow/underflow will result in a system reset.
Workaround 1:
Avoid a stack overflow/underflow e.g. by
- allocating a larger internal system stack (via bitfield STKSZ in register
SYSCON), or
- reducing the required stack space by reducing the number of interrupt levels, or
- testing in each task procedure whether a stack underflow is imminent, and
anticipating the stack refill procedure before executing the RETI instruction.
Errata Sheet C167-LM, ES-BB, BC, 1.1
-4/7-
Workaround 2:
Disable MULx instructions from being interrupted e.g. with the following
instruction sequence:
ATOMIC #1
MULx Rm, Rn
Workaround 3
(may be selected if
no divide
operations are used in an
interruptable program section):
In each interrupt service routine (task procedure), always clear bit MULIP in the
PSW and set register MDC to 0000h. This will cause an interrupted multiplication
to be completely restarted from the first cycle after return to the priority level on
which it was interrupted.
In case that an interrupt service routine is also using multiplication, only registers
MDH and MDL must be saved/restored when using this workaround, while bit
MULIP and register MDC must be set to zero.
Workarounds for C165/C167 in combination with C compilers are currently under
evaluation.
RST.1:
System Configuration via P0L.0 during Software/Watchdog
Timer Reset
When P0L.0 is externally pulled low at the end of the internal software or
watchdog timer reset sequence, the device will enter emulation mode. The other
pins P0L.5 .. P0L.1 are treated according to the description in the C167 User’s
Manual (chapter 17), i.e. they are disregarded during software or watchdog timer
reset.
Functional
Problem
ADC.8
CPU.8
CPU.9
CPU.11
RST.1
Table 1:
Short Description
CC31/ADC Interference
Jump instructions in EXTEND sequence
PEC Transfers during instruction execution from
Internal RAM
Stack Underflow Trap during Restart of interrupted
Multiply
System Configuration via P0L.0 during Software/
Watchdog Timer Reset
Functional Problems of the C167
Remarks
Errata Sheet C167-LM, ES-BB, BC, 1.1
-5/7-
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