MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MRFIC0912/D
The MRFIC Line
900 MHz GaAs
Integrated Power Amplifier
Designed primarily for use in high efficiency Analog Cellular applications,
the MRFIC0912 is a two–stage power amplifier in Motorola’s proprietary
Power Flat Pack 16–lead package. This integrated circuit requires minimal
off-chip matching while allowing for the maximum in flexibility in optimizing
gain and efficiency. The design employs Motorola’s planar, self–aligned GaAs
MESFET IC process to give the highest efficiency possible.
•
Usable Frequency Range = 800 – 1000 MHz, Specified for 824 – 905 MHz
•
30.8 dBm Minimum Output Power
•
470 mA Maximum Supply Current at 30.8 dBm Output
•
23.8 dB Minimum Gain
•
Simple Off–chip Matching for Maximum Power/Efficiency Flexibility
•
4.6 Volt Supply
•
45 dB/Volt Typical Power Output Control
•
Order MRFIC0912R2 for Tape and Reel Option.
R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.
•
Device Marking = M0912
MRFIC0912
900 MHz
GaAs INTEGRATED
POWER AMPLIFIER
ARCHIVE INFORMATION
CASE 978–02
(PFP–16)
GND
1
16
N/C
VG2
2
15
N/C
N/C
3
14
N/C
VD1
N/C
4
13
RF OUT/VD2
RF OUT/VD2
5
12
VG1
6
11
RF OUT/VD2
N/C
RF IN
7
10
N/C
8
9
GND
Pin Connections and Functional Block Diagram
REV 1
©
Motorola, Inc. 1997
MOTOROLA RF DEVICE DATA
MRFIC0912
1
ARCHIVE INFORMATION
MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Ratings
Supply Voltage
RF Input Power
Gate Voltage
Storage Temperature Range
Operating Case Temperature
Thermal Resistance, Junction to Case
Symbol
VD1, VD2
PRF
VG1, VG2, VGG
Tstg
TC
R
θJC
Limit
8
20
–5
– 65 to +150
– 35 to +100
18
Unit
Vdc
dBm
Vdc
°C
°C
°C/W
RECOMMENDED OPERATING RANGES
Parameter
RF Frequency
Symbol
fRF
VD1, VD2
VG1, VG2
Value
824–905
4.0–6.0
–2.3 to –1.5
Unit
MHz
ARCHIVE INFORMATION
Gate Voltage
Vdc
ELECTRICAL CHARACTERISTICS
(VD1, VD2 = 4.6 V, TA = 25°C, fRF = 840 MHz, Pin = 7 dBm, VGG set for ID2Q = 200 mA, Tested in
Circuit Shown in Figure 1)
Characteristic
RF Output Power
Power Slump (VD1, VD2 = 4.0 V, TC = 100
_
C)
Load Mismatch Survival (VD1, VD2 = 7 V, Load VSWR = 10:1, all phases,
10 sec)
Spurious Output (VD1,VD2 = 0 to 7 V, Pin = 5 to 9 dBm, Load
VSWR = 10:1)
Input Return Loss
Harmonic Output (Pout = 30.8 dBm)
2f0
3f0
4f0
Noise Power (VDD = 0 to 7 V, 45 MHz Above fRF at 30 kHz BW)
Maximum Power Control Voltage Slope (Change in Pout for Change on
VD1)
Total Supply Current (VD1 set for Pout = 30.8 dBm)
VGG Required for ID2Q = 200 mA
Gate Current during RF Operation
Min
30.8
28.5
Typ
31.2
—
No Degradation
Max
—
—
Unit
dBm
dBm
—
—
—
—
—
—
—
—
–2.3
–2
—
10
—
—
—
—
45
430
–2.0
—
–60
—
–25
–40
–40
–93
—
470
–1.7
2
dBc
dB
dBc
dBm
dB/V
mA
Vdc
mA
DESIGN AND APPLICATIONS INFORMATION
The MRFIC0912 has been designed for high efficiency
900 MHz applications such as analog cellular and Industrial,
Medical and Scientific (ISM) equipment. The two stage MES-
FET design utilizes Motorola’s planar refractory gate process
to allow high performance GaAs to be applied to consumer
applications. The proprietary PFP–16 package assures good
grounding and low thermal resistance.
As shown in Figure 1, the gate voltage pins can be ganged
together and one voltage applied to both gates to set the
quiescent operating current. Alternatively, VG1 and VG2 can
be set separately. VD1 can be used as power control with a
45 dB per volt sensitivity. The placement of C3 in the VD1
supply line can be varied to optimize RF performance since
T2 is part of a shunt L matching section. On the output, pins
11, 12 and 13, the placement of C11 is adjusted for best RF
performance.
Layout is important for amplifier stability and RF perfor-
mance. Ground vias must be located as close to circuit
ground connections as possible. Power supply bypassing
C3, C6, C9, and C10 must be included to reduce out–of–
band gain and prevent spurious output.
Evaluation Boards
Evaluation boards are available for RF Monolithic Inte-
grated Circuits by adding a “TF” suffix to the device type.
For a complete list of currently available boards and ones
in development for newly introduced product, please con-
tact your local Motorola Distributor or Sales Office.
MRFIC0912
2
MOTOROLA RF DEVICE DATA
ARCHIVE INFORMATION
Supply Voltage
Vdc
VGG
C5
1
2
VG2
3
C6 C3
T2
4
5
R1
6
C4
VG1
16
15
14
L2
13
12
T1
11
10
9
C11
C8
C9
C10
VD2
RF OUT
VD1
RF IN
ARCHIVE INFORMATION
C1
8
R1
1 kΩ
C1
3.3 pF
C2, C3, C8, C9 100 pF
C11
8.2 pF
C6
C10
C4, C5
L1
0.01
µF
1
µF
1000 pF
10 nH
L2
22 nH
T1
50
Ω,
13° @ 840 MHz
T2
50
Ω,
8° @ 840 MHz
BOARD MATERIAL — GLASS/EPOXY,
ε
r =
4.45, THICKNESS = 18 MIL
Figure 1. Applications Circuit Configuration
TYPICAL CHARACTERISTICS
35
VDD = 5.8 V
Pout , OUTPUT POWER (dBm)
Pout , OUTPUT POWER (dBm)
T = 25°C
30
85°C
25
30
VDD = 4.6 V
25
VDD = 4.0 V
35
20
f = 837 MHz
TEMP = 25°C
15
–10
–5
0
Pin, INPUT POWER (dBm)
5
10
20
– 35°C
VDD = 4.6 V
f = 837 MHz
15
–10
–5
0
Pin, INPUT POWER (dBm)
5
10
Figure 2. Output Power versus Input Power
Figure 3. Output Power versus Input Power
MOTOROLA RF DEVICE DATA
MRFIC0912
3
ARCHIVE INFORMATION
C2
L1
7
TYPICAL CHARACTERISTICS
35
VDD = 5.8 V
Pout , OUTPUT POWER (dBm)
25
VDD = 4.0 V
VDD = 4.6 V
Pout , OUTPUT POWER (dBm)
25
35
T = 25°C
85°C
15
15
– 35°C
5
f = 837 MHz
Pin = 7.0 dBm
TEMP = 25°C
0
1
3
2
4
Vcntrl, CONTROL VOLTAGE (VOLTS)
5
6
5
VDD = 4.6 V
f = 837 MHz
Pin = 7.0 dBm
0
1
–5
–5
ARCHIVE INFORMATION
Figure 4. Output Power versus Control Voltage
Figure 5. Output Power versus Control Voltage
70
PAE, POWER ADDED EFFICIENCY (%)
PAE, POWER ADDED EFFICIENCY (%)
60
50
40
30
20
10
0
–10
–5
VDD = 4.6 V
VDD = 5.8 V
0
Pin, INPUT POWER (dBm)
f = 837 MHz
TEMP = 25°C
5
10
VDD = 4.0 V
70
T = 25°C
60
85°C
50
40
30
20
10
0
–10
–5
0
Pin, INPUT POWER (dBm)
VDD = 4.6 V
f = 837 MHz
5
10
– 35°C
Figure 6. Power Added Efficiency versus
Input Power
Figure 7. Power Added Efficiency versus
Input Power
70
PAE, POWER ADDED EFFICIENCY (%)
60
50
40
30
VDD = 5.8 V
20
10
0
0
1
2
3
4
Vcntrl, CONTROL VOLTAGE (VOLTS)
5
6
f = 837 MHz
Pin = 7.0 dBm
TEMP = 25°C
VDD = 4.0 V
VDD = 4.6 V
PAE, POWER ADDED EFFICIENCY (%)
70
60
50
40
30
20
10
0
0
1
VDD = 4.6 V
f = 837 MHz
Pin = 7.0 dBm
2
3
4
Vcntrl, CONTROL VOLTAGE (VOLTS)
5
– 35°C
T = 25°C
85°C
Figure 8. Power Added Efficiency versus
Control Voltage
Figure 9. Power Added Efficiency versus
Control Voltage
MRFIC0912
4
MOTOROLA RF DEVICE DATA
ARCHIVE INFORMATION
2
3
4
Vcntrl, CONTROL VOLTAGE (VOLTS)
5
TYPICAL CHARACTERISTICS
34
VDD = 5.8 V
31.6
Pout , OUTPUT POWER (dBm)
Pout , OUTPUT POWER (dBm)
33
31.4
31.2
31
30.8
30.6
30.4
825
VDD = 4.6 V
Pin = 7.0 dBm
830
835
840
f, FREQUENCY (MHz)
845
85°C
T = 25°C
– 35°C
31.8
32
VDD = 4.6 V
31
VDD = 4.0 V
30
29
825
Pin = 7.0 dBm
TEMP = 25°C
830
835
840
f, FREQUENCY (MHz)
845
850
ARCHIVE INFORMATION
Figure 10. Output Power versus Frequency
Figure 11. Output Power versus Frequency
62
PAE, POWER ADDED EFFICIENCY (%)
PAE, POWER ADDED EFFICIENCY (%)
63
– 35°C
61
T = 25°C
VDD = 4.6 V
61
VDD = 4.0 V
60
VDD = 5.8 V
59
85°C
57
VDD = 4.6 V
Pin = 7.0 dBm
55
825
830
835
840
845
850
59
825
Pin = 7.0 dBm
TEMP = 25°C
830
835
840
845
850
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 12. Power Added Efficiency
versus Frequency
Figure 13. Power Added Efficiency
versus Frequency
450
400
I D1 , I D2 , DRAIN CURRENT (mA)
350
300
250
200
150
100
50
0
0
1
2
3
4
Vcntrl, CONTROL VOLTAGE (VOLTS)
5
ID1
VDD = 4.6 V
f = 837 MHz
Pin = 7.0 dBm
ID2
Figure 14. Drain Current versus Control
Voltage
MOTOROLA RF DEVICE DATA
MRFIC0912
5
ARCHIVE INFORMATION
850
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