1/4
Structure
Product Name
Product No.
Features
Silicon Monolithic Integrated Circuit
Sound Generator and AAC/AACplus decoder for cellular phone
BU8865GV
64 polyphony 128 sounds + drum set 47 sounds generation and ADPCM player
HE-AAC(AACplus) and AAC decoders support ISO/IEC 14496-3:2001
Package and Pin compatibility with BU8859GV(64 tones melody)
Register upper compatibility with BU8859GV
o
○Absolute
Maximum Ratings(Ta=25 C)
Parameter
Analog/PLL supply voltage
Digital I/O supply voltage
CORE supply voltage
Voltage applied to pins
Power dissipation
Storage temperature range
Operating temperature range
Symbol
AVDD
VDDIO
VDDCO
VIN
Pd
Tstg
Topr
Limits
-0.3
½
4.5
-0.3
½
4.5
-0.3
½
2.16
DVSS-0.3
½
VDDIO+0.3
490
*1
-50
½
125
-30
½
85
Unit
V
V
V
V
mW
℃
℃
Conditions
AVDD and PLLVDD
Warranty setting of single IC.
*1 When Ta is above 25℃, reduce 4.5mW per 1℃.
o
○Recommended
operating conditions(unless otherwise noted, Ta = 25 C)
Parameter
Symbol
Min
Ratings
Typ
3.0
3.0
1.5
25
-
-
50
-
Max
3.3
3.3
1.65
85
26
15
60
-
Unit
Conditions
Analog/PLL supply voltage
Digital I/O supply voltage
Digital CORE supply voltage
Ambient temperature
MCLK input frequency
SCLK input frequency
MCLK duty
Analog pin's load resistance
AVDD
VDDIO
VDDCO
Ta
FMCLK
FSCLK
DMCLK
RL
2.7
VDDCO
1.35
-30
2.688
-
40
10
V
V
V
℃
MHz
MHz
%
kΩ
AVDD and PLLVDD
Core clock > 30MHz
This chip is not designed to protect itself against radioactive rays.
REV. A
2/4
○Electrical
Characteristics
o
(unless otherwise noted, Ta = 25 C)
Parameter
Symbol
Min
rating
Typ
Max
Unit
Conditions
Digital DC characteristics
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Analog DC characteristics
F pin voltage
Analog pin voltage
General characteristics
VREF pin rise time
Analog pin characteristics
Analog amplitude
Power consumption
Analog Idd1
(AVDD)
PLL Idd1
(PLLVDD)
Digital Idd11
(DVDD_CORE)
Digital Idd12
(DVDD_IO)
Analog Idd2
(AVDD)
PLL Idd2
(PLLVDD)
Digital Idd21
(DVDD_CORE)
Digital Idd22
(DVDD_IO)
VMAX
-
0.6AVDD
-
Vp-p
Theoretical value
for dynamic range
Playing
Playing AACplus
Playing AACplus
Playing(not using
Digital Output)
Standby mode
Standby mode
Standby mode
Standby mode
TRVR
-
20
30
mS
CVREF = 1uF,
NRST=L
→
H
VAGND
VOUT
0.475AVDD
0.47AVDD
0.5AVDD
0.5AVDD
0.525AVDD
0.53AVDD
V
V
IOUT=0A(noload)
IOUT=0A(noload)
Not playing
VIH
VIL
IIH
IIL
VOH
VOL
DVDD_IO-0.5
-
-
-1
DVDD_IO-0.3
-
-
-
-
-
-
-
-
DVSS+0.5
1
-
-
DVSS+0.3
V
V
uA
uA
V
V
VIH=VDDIO
VIL=DVSS
IOH=-0.8mA
IOL=0.8mA
DVDD_CORE=1.5[V], DVDD_IO=3.0[V], AVDD=3.0[V]
AIDD1
-
1.7
2.5
PIDD1
DIDD11
DIDD12
AIDD2
PIDD2
DIDD21
DIDD22
-
-
-
-
-
-
-
0.6
15.5
0.9
-
-
-
-
1.5
20
1
2
1
30
10
mA
mA
mA
mA
uA
uA
uA
uA
REV. A
3/4
○External
measure and View
1PIN
MARK
6.0±0.1
0.23
1.2MAX
6.0±0.1
BU8859
65
Lot No.
S
0.10 S
P=0.65x7
0.725±0.1
0.65
A
63-φ0.33±0.05
φ0.08
M
S AB
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8
.725±0.1
P=0.65x7
B
0.65
(UNIT: mm)
○Pin
layout diagram
Pin
Pin name
NO.
A1
NC
A2
LED1
A3
LED3
A4
NC
A5
DVSS
A6
MCLK2
A7
DVDD_IO
A8
NC
B1
D2
B2
D0
B3
LED2
B4
DVDD_CORE
B5
NC
B6
MCLK1
B7
PLLVSS
B8
PLLVDD
C1
NC
C2
D3
C3
VIB
C4
NC
C5
NC
C6
PLL_FILTER
C7
NC
C8
IFSEL
D1
DVSS
D2
CD
D3
DVDD_IO
D4
D1
D5
NRST
D6
NC
D7
TMODE2
D8
NC
Pin
NO.
Pin name
NC
DVDD_CORE
NC
SCLK
AVSS
TMODE0
NC
TMODE1
D4
D5
D7
DACMCK
NC
NC
MONO_OUT
NC
D6
SIO
SEL
NC
DIGCK
NC
AVDD
VREF
NC
SO
INT
DIGDT
DIGLR
L_OUT
R_OUT
NC
E1
E2
E3
E4
E5
E6
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
D
D
SBGA063T060
○Block
diagram
MIDI Core
Sequencer Core
LED 3ch/VIB
D7½D0
IFSEL
SO(/WR)
SIO(/A0)
SCLK(/RD)
MIDI FIFO
UCS
Parameter
Sequencer
CPU
Each ch
Status
Voice
Parameter
L/R
Output
FIFO
Program
ROM
Parametric
Equlizer
Mix/Select
and Over-
sampling
LED,VIB
Control
LED1½3
VIB
MIDI
DSP
UCS
RAM
Hard Logic for
MIDI
Wave
ROM
Digital
Audio
Output
Standard/IIS
SEL
DIGLR
DIGDT
DIGCK
DACMCK
CPU I/F
SEL(/CS)
Master ch
FIFO
INT
Slave ch
FIFO
NRST
ADPCM Core
Digital
filter
D/A
Converter
VREF
L_OUT
R_OUT
MONO_OUT
ADPCM/PCM
Decoder
DSP
AAC Decoder Core
Bitstream Input
FIFO
AAC/
AACplus
Decoder
L/R
Output
FIFO
Clock Control
Sampling Clock
Timing Generator
test
TMODE0½2
PLL
PLL_FILTER
MCLK1
MCLK2
REV. A
4/4
○
Cautions on use
(1) Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any
special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety
measures including the use of fuses, etc.
(2) Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The
electrical characteristics are guaranteed under the conditions of each parameter.
(3) Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the
breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s
power supply terminal.
(4) Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for
the digital block power supply and the analog block power supply, even though these power supplies has the same level of
potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the
diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For
the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At
the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be
used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant.
(5) GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.
Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric
transient.
(6) Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can
break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between
the terminal and the power supply or the GND terminal, the ICs can break down.
(7) Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
(8) Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress.
Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set
PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the
jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In
addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to
the transportation and the storage of the set PCB.
(9)Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the
parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the
input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals
a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage
to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is
applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
(10) Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
(11) External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a
degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
(12) Others
In case of use this LSI, please peruse some other detail documents, we called ,Technical note, Functional description,
Application note.
REV. A
Appendix
Notes
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The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
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upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no re-
sponsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
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or devices (such as audio visual equipment, office-automation equipment, communication devices, elec-
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malfunction for a variety of reasons.
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Appendix-Rev4.0