CAT130044
Voltage Supervisor with
Watchdog Timer and
Microwire Serial EEPROM
Description
CAT130044 is a voltage supervisor with a watchdog timer and serial
EEPROM. This device generates a 140 ms reset pulse whenever the
supply voltage falls below a preset threshold, or when there is no
activity on the CS pin for 1.6 seconds. It also contains 4 kbits of
EEPROM that can be written and read using the standard Microwire
serial protocol.
Features
http://onsemi.com
SOIC−8
W SUFFIX
CASE 751BD
•
•
•
•
•
•
•
•
•
•
•
•
Accurate Under Voltage System Monitoring
High Speed Operation: 2 MHz
1.8 V to 5.5 V Supply Voltage Range
Reset Output Valid with Vcc > 1 V
Sequential Read
Software Write Protection
Power−up Inadvertent Write Protection
1,000,000 Program/Erase Cycles
100 Year Data Retention
Operating Range from
−40°C
to +85°C
8−lead Package
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
SK
DI
PIN CONFIGURATION
CS 1
SK 2
DI 3
DO 4
8 V
CC
7 RST
6 RSTB
5 GND
SOIC (W)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
EEPROM
ARRAY
V
CC
LEVEL SENSE
&
TIMER
TIMEOUT
COMPARATOR
DO
CS
RSTB
V
CC
V
CC
TOLERANCE
BIAS
+
–
DIGITAL
DELAY
V
CC
VOLTAGE
REFERENCE
GND
RST
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2012
May, 2012
−
Rev. 0
1
Publication Order Number:
CAT130044/D
CAT130044
Table 1. PIN FUNCTION
Pin Name
CS
SK
DI
DO
Function
Chip Select and Watchdog Monitor Input
Clock Input
Serial Data Input
Serial Data Output
Pin Name
V
CC
GND
RST
RSTB
Power Supply
Ground
Reset output (high)
Reset output (low)
Function
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
−65
to +150
−0.3
to +6.0
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 3. ELECTRICAL OPERATING CHARACTERISTICS
(DC Characteristics: V
CC
= 2.0 V to 3.6 V,
−40°C
≤
T
A
≤
+85°C unless
otherwise noted. Typical Values at T
A
= 25°C and V
CC
= 3.0 V.) (Note 2)
Symbol
V
RST
Parameter
Reset Threshold
Reset Threshold Tempco
Reset Threshold Hysteresis
t
RD
t
RP
V
OH
V
OL
V
CC
to Reset Delay (Note 3)
Reset Active Timeout Period
RSTB Output High Voltage
RSTB Output Low Voltage
V
CC
= V
RST max
, I
SOURCE
=
−30
mA
V
CC
= V
RST min
, I
SINK
= 1.2 mA
T
A
= 0°C to +70°C, V
CC
= 1 V,
V
CC
falling, I
SINK
= 50
mA
T
A
= T
MIN
to T
MAX
, V
CC
= 1.2 V,
V
CC
falling, I
SINK
= 100
mA
I
SOURCE
V
OH
V
OL
WATCHDOG INPUT
t
WD
t
WDI
Watchdog Timeout Period
CS Pulse Width
CS Input Current (Note 4)
V
IL
= 0.4 V, V
IH
= 0.8 x V
CC
CS = V
CC
, Time Average
CS = 0 V, Time Average
−20
1.12
50
120
−15
160
1.60
3.20
s
ns
mA
RSTB Output
Short−Circuit Current
RST Output Voltage
Reset = 0 V, V
CC
= 5.5 V
Reset = 0 V, V
CC
= 3.6 V
V
CC
> 1.8 V, I
SOURCE
=
−150
mA
V
CC
= V
RST max
, I
SINK
= 1.2 mA
0.8 x V
CC
0.3
V
CC
= V
TH
to (V
TH
−
100 mV)
140
0.8 x V
CC
0.3
0.3
0.3
1.5
0.8
V
mA
CAT130044, R option
Conditions
Min
2.55
Typ
2.63
40
5
20
200
400
Max
2.70
Units
V
ppm/°C
mV
ms
ms
V
V
2. Over−temperature limits are guaranteed by design and not production tested.
3. The RESET short−circuit current is the maximum pull−up current when reset is driven low by a bidirectional output.
4. The CS input current is specified as an average input current when the CS input is driven high or low. To clock the CS input in the active
mode the drive device must be able to source or sink at least 200
mA
when active.
http://onsemi.com
2
CAT130044
Table 4. SERIAL EEPROM RELIABILITY CHARACTERISTICS
(Note 5)
Symbol
N
END
(Note 6)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. Block Mode, V
CC
= 5 V, 25°C.
Table 5. SERIAL EEPROM D.C. OPERATING CHARACTERISTICS
(
V
CC
= +1.8 V to +5.5 V, T
A
=
−40°C
to +85°C unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB1
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1:DO
V
OH1:DO
V
OL2:DO
V
OH2:DO
Parameter
Power Supply Current (Write)
Power Supply Current (Read)
Power Supply Current (Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
DO Output Low Voltage
DO Output High Voltage
DO Output Low Voltage
DO Output High Voltage
Test Conditions
f
SK
= 1 MHz, V
CC
= 5.0 V
f
SK
= 1 MHz, V
CC
= 5.0 V
V
IN
= GND or V
CC
, CS = GND
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
, CS = GND
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
1.8 V
≤
V
CC
< 4.5 V
1.8 V
≤
V
CC
< 4.5 V
4.5 V
≤
V
CC
< 5.5 V, I
OL
= 2.1 mA
4.5 V
≤
V
CC
< 5.5 V, I
OH
=
−400
mA
1.8 V
≤
V
CC
< 4.5 V, I
OL
= 1 mA
1.8 V
≤
V
CC
< 4.5 V, I
OH
=
−100
mA
Min
Max
1
500
20
1
1
Units
mA
mA
mA
mA
mA
V
V
V
V
V
V
−0.1
2
0
V
CC
x 0.7
2.4
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
0.2
V
CC
−
0.2
V
V
Table 6. PIN CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
C
OUT
(Note 7)
C
IN
(Note 7)
Test
Output Capacitance (DO)
Input Capacitance (SK, DI)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
7. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
http://onsemi.com
3
CAT130044
Table 7. SERIAL EEPROM A.C. CHARACTERISTICS
(V
CC
= +1.8 V to +5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.) (Note 8)
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 9)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2000
Parameter
Min
50
0
100
100
0.25
0.25
100
5
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
8. Test conditions according to “A.C. Test Conditions” table.
9. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
Table 8. SERIAL EEPROM POWER−UP TIMING
(Notes 10, 11)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
10. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
11. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 9. SERIAL EEPROM A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V
CC
to 0.7 V
CC
0.5 V
CC
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
1.8 V
≤
V
CC
≤
4.5 V
1.8 V
≤
V
CC
≤
4.5 V
Current Source I
OLmax
/I
OHmax
; CL = 100 pF
http://onsemi.com
4
CAT130044
Device Operation
Processor RESET
Watchdog Timer
The CAT130044 detects supply voltage (V
CC
) conditions
that are below the specified voltage trip value (V
RST
) and
provide a reset output to maintain correct system operation.
On power−up, RST and RSTB are kept active for a
minimum delay tRP of 140 ms after the supply voltage
(V
CC
) rises above V
RST
to allow the power supply and
processor to stabilize. When V
CC
drops below the voltage
trip value (V
RST
), the reset output signals RST and RSTB
are pulled active. RST and RSTB specifically designed to
provide the reset input signals for processors. This provides
reliable and consistent operation as power is turned on, off
or during brownout conditions by maintaining the processor
operation in known conditions.
The CAT130044 uses the Chip Select input as a Watchdog
input. The watchdog timer function forces the RST and
RSTB signals active when the CS input does not have a
transition from low−to−high or high−to−low within 1.12
seconds. Timeout of the watchdog starts when RST and
RSTB become inactive. If a transition occurs on the CS input
pin prior to the watchdog time−out, the watchdog timer is
reset and begins to time−out again. If the watchdog timer is
allowed to time−out, then the reset outputs will go active for
t
RP
and once released will repeat the watchdog timeout
process.
Figure below shows a typical implementation of a
watchdog function. Any processor signal that repeats
dependant on the normal operation of the processor or
directed by the software operating on the processor can be
used to strobe the watchdog input.
For the most efficient operation the CS input should be
held low the majority of the time and only strobed high as
required to reset the watchdog timer.
INDETERMINATE
STROBE
INVALID
STROBE
WDI
VALID
STROBE
t
WD
MIN.
MAX.
RSTB
Figure 2. Timing Diagram – Strobe Input
http://onsemi.com
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
