HY5V22GF
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY5V22G is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY5V22G is organized as 4banks of 1,048,576x32.
HY5V22G is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
•
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
•
•
Internal four banks operation
•
Burst Read Single Write operation
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
ORDERING INFORMATION
Part No.
HY5V22GF-H
HY5V22GF-P
Clock Frequency
133MHz
Power
Normal
Organization
4Banks x 1Mbits
x32
Interface
LVTTL
Package
90Ball FBGA
100MHz
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3/Nov. 01
HY5V22GF
PIN CONFIGURATION
1
A
D Q 26
D Q 24
VSS
VDD
DQ 23
DQ 21
2
3
4
5
6
7
8
9
B
D Q 28
VD DQ
VSS Q
VDD Q
VSS Q
DQ 19
C
V SSQ
D Q 27
DQ 25
DQ 22
DQ 20
VD DQ
D
V SSQ
D Q 29
DQ 30
DQ 17
DQ 18
VD DQ
E
VDD Q
D Q 31
NC
NC
DQ 16
VSS Q
F
VSS
DQM3
A3
A2
DQM2
VD D
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
Top View
(11m m x13m m )
NC
BA1
A11
J
C LK
CK E
A9
BA0
CS#
RAS #
K
DQM1
NC
NC
C AS#
W E#
DQM0
L
VD DQ
DQ8
VSS
VD D
DQ7
VSSQ
M
VSS Q
DQ 10
DQ 9
DQ 6
DQ5
VD D Q
N
VSS Q
DQ 12
D Q 14
DQ 1
DQ3
VD D Q
P
DQ 11
VD DQ
V SSQ
VD DQ
VSSQ
DQ4
R
DQ 13
DQ 15
VSS
VDD
DQ 0
DQ2
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.3/Nov. 01
3
HY5V22GF
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
Row Active
1M x32 Bank 3
Row
Pre
Decoder
1M x32 Bank 2
X decoder
1M x32 Bank 1
X decoder
1M x32 Bank 0
X decoder
DQ0
DQ1
I/O Buffer & Logic
Sense AMP & I/O Gate
State Machine
Column
Active
X decoder
Memory
Cell
Array
Column
Pre
Decoder
Y decoder
DQ30
DQ31
Bank Select
Column Add
Counter
A0
A1
Address buffers
A10
BA0
BA1
Address
Register
Burst
Counter
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.3/Nov. 01
4
HY5V22GF
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD,
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260
⋅
10
Rating
°C
°C
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
(TA=0 to 70°C)
Parameter
Power Supply Voltage
Input high voltage
Input low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
3.0
2.0
V
SSQ
- 0.3
Typ.
3.3
3.0
0
Max
3.6
V
DDQ
+ 0.3
0.8
Unit
V
V
V
Note
1,2
1,3
1,4
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
DD/
V
DDQ
(min) is 3.15V for HY5V22GF-H/P
3.V
IH
(max) is acceptable 5.6V AC pulse width with
≤3ns
of duration with no input clamp diodes
4.V
IL
(min) is acceptable -2.0V AC pulse width with
≤3ns
of duration with no input clamp diodes
AC OPERATING CONDITION
(TA=0 to 70°C, 3.0V
≤V
DD
≤3.6V,
V
SS
=0V - Note1)
Parameter
AC input high / low level voltage
Input timing measurement reference level voltage
Input rise / fall time
Output timing measurement reference level
Output load capacitance for access time measurement
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
CL
Value
2.4/0.4
1.4
1
1.4
30
Unit
V
V
ns
V
pF
2
Note
Note :
1.3.15V
≤V
DD
≤3.6V
is applied for HY5V22GF-H/P
2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Rev. 0.3/Nov. 01
5
HY5V22GF
CAPACITANCE
(TA=25°C, f=1MHz, VDD=3.3V)
Parameter
Input capacitance
CLK
A0 ~ A10, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
Data input / output capacitance
DQ0 ~ DQ31
Pin
Symbol
C
I1
CI
2
C
I/O
Min
2.5
2.5
4
Max
3.5
3.8
6.5
Unit
pF
pF
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
Vtt=1.4V
RT=500
Ω
RT=50
Ω
Output
30pF
Output
Z0 = 50Ω
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I
(DC operating conditions unless otherwise noted)
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
I
LI
I
LO
V
OH
V
OL
Symbol
Min.
-1
-1
2.4
-
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
I
OH
= -2mA
I
OL
= +2mA
Note :
1.V
IN
= 0 to 3.6V, All other pins are not under test = 0V
2.D
OUT
is disabled, V
OUT
=0 to 3.6V
Rev. 0.3/Nov. 01
6
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