Features
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26-42 MIPS Integer Performance
3.5-5.6 MFLOPS Floating-Point-Performance
IEEE 754-Compatible FPU
Independent Instruction and Data MMUs
4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed
Simultaneously
32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
Multimaster/Multiprocessor Support via Bus Snooping
Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize
Throughput
4G bytes Direct Addressing Range
Software Support Including Optimizing C Compiler and UNIX
®
System V Port
IEEE P 1149-1 Test Mode (JTAG)
f = 25 MHz, 33 MHz; V
CC
= 5V ± 5%; P
D
= 7W
The Use of the TS88915T Clock Driver is Suggested
Third-
Generation
32-bit
Microprocessor
TS68040
Description
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-
bit microprocessors. The TS68040 is a virtual memory microprocessor employing
multiple, concurrent execution units and a highly integrated architecture to provide
very high performance in a monolithic HCMOS device. On a single chip, the TS68040
integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit
(FPU), and fully independent instruction and data demand-paged memory manage-
ment units (MMUs), including 4K bytes independent instruction and data caches. A
high degree of instruction execution parallelism is achieved through the use of multi-
ple independent execution pipelines, multiple internal buses, and a full internal
Harvard architecture, including separate physical caches for both instruction and data
accesses. The TS68040 also directly supports cache coherency in multimaster appli-
cations with dedicated on-chip bus snooping logic.
The TS68040 is user-object-code compatible with previous members of the TS68000
Family and is specifically optimized to reduce the execution time of compiler-gener-
ated code. The 68040 HCMOS technology, provides an ideal balance between speed,
power, and physical device size.
Figure 1 is a simplified block diagram of the TS68040. Instruction execution is pipe-
lined in both the integer unit and FPU. Independent data and instruction MMUs control
the main caches and the address translation caches (ATCs). The ATCs speed up log-
ical-to-physical address translations by storing recently used translations. The bus
snooper circuit ensures cache coherency in multimaster and multiprocessing
applications.
Screening
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MIL-STD-883
DESC. Drawing 5962-93143
Atmel Standards
Rev. 2116A–HIREL–09/02
1
R suffix
PGA 179
Ceramic Pin Grid Array
Cavity Down
F suffix
CQFP 196
Gullwing Shape Lead
Ceramic Quad Fla Pack
Figure 1.
Block Diagram
INSTRUCTION DATA BUS
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
ADDRESS
INSTRUCTION
FETCH
CONVERT
DECODE
EFFECTIVE
ADDRESS
CALCULATE
EFFECTIVE
ADDRESS
FETCH
EXECUTE
WRITE
BACK
WRITE
BACK
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION MEMORY UNIT
B
U
S
C
O
N
T
R
O
L
L
E
R
ADDRESS
BUS
EXECUTE
DATA
BUS
DATA MEMORY UNIT
DATA
MMU/CACHE/SNOOP
CONTROLLER
DATA
ADDRESS
BUS
CONTROL
SIGNALS
FLOATING-
POINT
UNIT
INTEGER
UNIT
DATA
ATC
DATA
CACHE
OPERAND DATA BUS
2
TS68040
2116A–HIREL–09/02
TS68040
Introduction
The TS68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the inte-
ger unit processing capabilities of the TS68030 microprocessor with independent
4K bytes data and instruction caches and an on-chip FPU. The TS68040 maintains the
32-bit registers available with the entire TS68000 Family as well as the 32-bit address
and data paths, rich instruction set, and versatile addressing modes. Instruction execu-
tion proceeds in parallel with accesses to the internal caches, MMU operations, and bus
controller activity. Additionally, the integer unit is optimized for high-level language
environments.
The TS68040 FPU is user-object-code compatible with the TS68882 floating-point
coprocessor and conforms to the ANSI/IEEE Standard 754 for binary floating-point arith-
metic. The FPU has been optimized to execute the most commonly used subset of the
TS68882 instruction set, and includes additional instruction formats for single and dou-
ble-precision rounding of results. Floating-point instructions in the FPU execute
concurrently with integer instructions in the integer unit.
The MMUs support multiprocessing, virtual memory systems by translating logical
addresses to physical addresses using translation tables stored in memory. The MMUs
store recently used address mappings in two separate ATCs-on-chip. When an ATC
contains the physical address for a bus cycle requested by the processor, a translation
table search is avoided and the physical address is supplied immediately, incurring no
delay for address translation. Each MMU has two transparent translation registers avail-
able that define a one-to-one mapping for address space segments ranging in size from
16M bytes to 4G bytes each.
Each MMU provides read-only and supervisor-only protections on a page basis. Also,
processes can be given isolated address spaces by assigning each a unique table
structure and updating the root pointer upon a task swap. Isolated address spaces pro-
tect the integrity of independent processes.
The instruction and data caches operate independently from the rest of the machine,
storing information for fast access by the execution units. Each cache resides on its own
internal address bus and internal data bus, allowing simultaneous access to both. The
data cache provides write through or copyback write modes that can be configured on a
page-by-page basis.
The TS68040 bus controller supports a high-speed, non multiplexed, synchronous
external bus interface, which allows the following transfer sizes: byte, word (2 bytes),
long word (4 bytes), and line (16 bytes). Line accesses are performed using burst trans-
fers for both reads and writes to provide high data transfer rates.
3
2116A–HIREL–09/02
Pin Assignments
PGA 179
Figure 2.
Bottom View
Table 1.
Power Supply Affectation to PGA Body
GND
PLL
Internal Logic
Output Drivers
C6, C7, C9, C11,C13, K3, K16, L3, M16, R4, R11, R13,
S10, T4, S9, R6, R10
B2, B4, B6, B8, B10, B13, B15, B17, D2, D17, F2, F17,
H2, H17, L2, L17, N2, N17, Q2, Q17, S2, S15, S17
V
CC
S8
C5, C8, C10, C12, C14, H3, H16, J3, J16, L16, M3, R5,
R12, R8
B5, B9, B14, C2, C17, G2, G17, M2, M17, R2, R17,
S16
4
TS68040
2116A–HIREL–09/02
TS68040
CQFP 196
Figure 3.
Pin Assignments
Table 2.
Power Supply Affectation to CQFP Body
GND
PLL
Internal Logic
Output Drivers
4, 9, 10, 19, 32, 45, 73, 88, 113, 119, 121, 122, 124,
125, 129, 130, 141, 159, 172
7, 15, 22, 28, 35, 42, 49, 50, 51, 57, 63, 69, 76, 77, 83,
84, 91, 97, 98, 99, 105, 106, 146, 147, 148, 149, 155,
162, 163, 169, 176, 182, 183, 189, 195, 196
V
CC
127
3, 18, 31, 40, 46, 60, 72, 87, 114, 126, 137, 158, 173,
186
12, 25, 38, 54, 66, 80, 94, 102, 152, 166, 179, 192
5
2116A–HIREL–09/02
FPGA/CPLD
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