MX29F400T/B
4M-BIT [512Kx8/256Kx16] CMOS FLASH MEMORY
FEATURES
• 524,288 x 8/262,144 x 16 switchable
• Single power supply operation
- 5.0V only operation for read, erase and program
operation
• Fast access time: 55/70/90/120ns
• Low power consumption
- 40mA maximum active current(5MHz)
- 1uA typical standby current
• Command register architecture
- Byte/word Programming (7us/12us typical)
- Sector Erase (Sector structure 16K-Bytex1, 8K-
Bytex2, 32K-Bytex1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends an erase operation to read data from, or
program data to, another sector that is not being
erased, then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program and
•
erase cycle completion.
Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase cycle completion.
- Sector protect/unprotect for 5V only system or 5V/
12V system.
Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 44-pin SOP
- 48-pin TSOP
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
20 years data retention
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GENERAL DESCRIPTION
The MX29F400T/B is a 4-mega bit Flash memory orga-
nized as 512K bytes of 8 bits or 256K words of 16 bits.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory. The MX29F400T/B is packaged in 44-pin SOP,
48-pin TSOP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29F400T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29F400T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F400T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29F400T/B uses a 5.0V±10% VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0439
REV. 1.9 , APR. 03, 2002
1
MX29F400T/B
PIN CONFIGURATIONS
44 SOP(500 mil)
NC
RY/BY
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
PIN DESCRIPTION
SYMBOL
A0~A17
Q0~Q14
Q15/A-1
CE
WE
BYTE
RESET
OE
RY/BY
VCC
GND
PIN NAME
Address Input
Data Input/Output
Q15(Word mode)/LSB addr(Byte mode)
Chip Enable Input
Write Enable Input
Word/Byte Selection input
Hardware Reset Pin/Sector Protect Unlock
Output Enable Input
Ready/Busy Output
Power Supply Pin (+5V)
Ground Pin
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
48 TSOP (Standard Type) (12mm x 20mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX29F400T/B
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
MX29F400T/B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
P/N:PM0439
REV. 1.9, APR. 03, 2002
2
MX29F400T/B
SECTOR STRUCTURE
MX29F400T TOP BOOT SECTOR ADDRESS TABLE
Sector Size
(Kbytes/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
8/4
16/8
Address Range (in hexadecimal)
(x8)
(x16)
Address Range
Address Range
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-77FFFh
78000h-79FFFh
7A000h-7BFFFh
7C000h-7FFFFh
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3BFFFh
3C000h-3CFFFh
3D000h-3DFFFh
3E000h-3FFFFh
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
A17
0
0
0
0
1
1
1
1
1
1
1
A16
0
0
1
1
0
0
1
1
1
1
1
A15
0
1
0
1
0
1
0
1
1
1
1
A14
X
X
X
X
X
X
X
0
1
1
1
A13
X
X
X
X
X
X
X
X
0
0
1
A12
X
X
X
X
X
X
X
X
0
1
X
MX29F400B BOTTOM BOOT SECTOR ADDRESS TABLE
Sector Size
(Kbytes/
Kwords)
16/8
8/4
8/4
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Address Range (in hexadecimal)
(x8)
(x16)
Address Range
Address Range
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
A17
0
0
0
0
0
0
0
1
1
1
1
A16
0
0
0
0
0
1
1
0
0
1
1
A15
0
0
0
0
1
0
1
0
1
0
1
A14
0
0
0
1
X
X
X
X
X
X
X
A13
0
1
1
X
X
X
X
X
X
X
X
A12
X
0
1
X
X
X
X
X
X
X
X
Note:
Address range is A17~A-1 in byte mode and A17~A0 in word mode.
P/N:PM0439
REV. 1.9, APR. 03, 2002
3
MX29F400T/B
BLOCK DIAGRAM
CE
OE
WE
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
MX29F400T/B
X-DECODER
REGISTER
ARRAY
SOURCE
HV
ADDRESS
LATCH
A0-A17
FLASH
ARRAY
AND
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
Y-DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM0439
REV. 1.9, APR. 03, 2002
4
MX29F400T/B
AUTOMATIC PROGRAMMING
The MX29F400T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29F400T/B is less than 4 sec-
onds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F400T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 4 second. The Automatic Erase algorithm au-
tomatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29F400T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con-
trolled internally within the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation.
P/N:PM0439
REV. 1.9, APR. 03, 2002
5
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