GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
100-Pin TQFP & 165-bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
250 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
is a DCD (Dual Cycle Deselect) pipelined synchronous
SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the
same degree as read commands. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock.
Functional Description
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
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om
Applications
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
is a 9,437,184-bit high performance synchronous SRAM with
a 2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
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Paramter Synopsis
-333
-300
2.5
3.3
230
265
5.0
5.0
185
210
d
fo
r
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (V
DDQ
) pins are
used to decouple output noise from the internal circuits and are
3.3 V and 2.5 V compatible.
N
-250
2.5
4.0
200
230
5.5
5.5
160
185
ew
-200
3.0
5.0
170
195
6.5
6.5
140
160
D
3.8
6.7
140
160
7.5
7.5
128
145
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
3.0
250
290
4.5
4.5
200
230
Flow Through
2-1-1-1
Rev: 1.04a 3/2009
1/39
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-150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Unit
ns
ns
mA
mA
ns
ns
mA
mA
© 2002, GSI Technology
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
NC
BW
B
A
, B
B,
B
C
, B
D
NC
CK
GW
E
2
E
1
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
Type
I
I
I/O
—
I
I
—
I
I
I
I
I
I
I
I
I
I
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active high
Address Strobe (Processor, Cache Controller); active low
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Rev: 1.04a 3/2009
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Burst address counter advance enable; active low
Sleep Mode control; active high
Core power supply
I/O and Core Ground
Output driver power supply
Linear Burst Order mode; active low
N
Chip Enable; active low
Output Enable; active low
ew
D
es
Byte Write Enable for DQ Data I/Os; active low
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 2002, GSI Technology
FPGA/CPLD
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