GS880F18/32/36BT-5.5/6/6.5/7/7.5/8.5
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• Flow Through mode operation; Pin 14 = No Connect
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
-5.5
Flow
Through
2-1-1-1
3.3 V
2.5 V
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Curr
(x18)
Curr
(x32/x36)
5.5
5.5
175
200
175
200
-6
6.0
6.0
165
190
165
190
-6.5
6.5
6.5
160
180
160
180
-7
7.0
7.0
150
170
150
170
-7.5 -8.5 Unit
7.5
7.5
145
165
145
165
8.5
8.5
135
150
135
150
ns
ns
mA
mA
mA
mA
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
5.5 ns–8.5 ns
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with V
SS
connected to the FT pin location
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Functional Description
Applications
The GS880F18/32/36BT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Core and Interface Voltages
The GS880F18/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
Rev: 1.00b 12/2002
1/22
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-5.5/6/6.5/7/7.5/8.5
TQFP Pin Description
Symbol
A
0
, A
1
A
2
–A
17
A
18
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
NC
BW
B
A
, B
B,
B
C
, B
D
CK
GW
E
1
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
Type
I
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Input
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.00b 12/2002
5/22
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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