www.fairchildsemi.com
FAN7527
Power Factor Correction Controller
Features
• Internal Startup Timer
• Internal R/C filter eliminates the Need for an External
R/C filter
• Very Precise Adjustable Output Over Voltage Protection
• Zero Current Detector
• One Quadrant Multiplier
• Trimmed 1.5% Internal Bandgap Reference
• Under Voltage Lock Out with 3V of Hysteresis
• Totem Pole Output with High State Clamp
• Low Startup and Operating Current
• 8-Pin DIP or 8-Pin SOP
Description
The FAN7527 provides simple and high performance active
power factor correction. FAN7527 is optimized for
electronic ballast and low power, high density power
supplies which require minimum board area reduced
component count and low power dissipation. Internal R/C
filter eliminates the need for an external R/C filter. Internally
clamping the error amplifier and multiplier outputs,
improves turn on overshoot characteristics and current
limiting. Special circuitry has also been added to prevent no
load runaway conditions. Independent of supply voltage, the
output drive clamping circuit limits overshoot of the power
MOSFET gate drive. This greatly enhances the system
reliability.
8-DIP
Applications
• Electronic Ballast
• SMPS
1
8-SOP
1
Rev 1.0.3
©2001 Fairchild Semiconductor Corporation
FAN7527
Internal Block Diagram
Vcc
8
2.5V Ref
Vcc
+
-
12V
↔
9V
UVLO
Internal
Internal
Bias
Drive
Output
Timer R
S
7
OUT
Idet
5
6.5V
7.2V
2V
↔
1.5V
+
-
Zero Current
Detector
Static OVP
40K
Q
CS
4
8pF
+
R
+
2.25V
-
Current Sense
Comparator
1.8V
Vref
Veao(L) = 2.25V
Vmo
-
Vm1
+
Vm2
Multiplier
0.25V
-
+
-
Vref ~ Vref+2.5V
Isovp=30uA
Idovp=40uA
Vref
MULT 3
0 ~ 3.8V
Vea(-)
Error Amp
1
INV
K =
Vmo
Vm1 * (Vm2-Vref)
GND
OVP Current
Detector
6
GND
2
EA_OUT
2
FAN7527
PIN Description
INV
1
2
3
4
(Top View)
8
7
6
5
Vcc
OUT
GND
ldet
EA_OUT
MULT
CS
Pin Number
1
2
3
Pin Name
INV
EA_OUT
MULT
Pin Function Descrition
Inverting input of the error amplifier. The output of the boost converter
should be resistively divided to 2.5V and connected to this pin.
The output of the error amplifier. A feedback conpensation network is
placed between this pin and the INV pin.
Input to the multiplier stage. The full-wave rectified AC is devided to
less than 2V and is connected to this pin.
Input to the PWM comparator. Current is sensed in the boost stage
MOSFET by a resistor in the source lead. An internal leading edge
blanking circuitry has been included to reject any high frequency noise
present on the current waveform.
The zero current detector senses the inductor current by monitoring
when the boost inductor auxilary winding voltage falls below 1.8V. If it
is connected to GND, the device is disabled.
The ground potential of all the pins.
Gate driver output . A push pull output stage is able to drive the Power
MOSFET with peak current of 400mA.
Supply voltage of driver and control circuits.
4
5
CS
ldet
6
7
8
GND
OUT
Vcc
3
FAN7527
Absolute Maximum Ratings (Ta=25°C)
°
Characteristics
Supply Voltage
Peak Drive Output Current
Driver Output Clamping Diodes Vo > Vcc or Vo < -0.3V
Detector Clamping Diodes
Error Amp, Multiplier And Comparator Input Voltages
Operating Junction Temperature
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Symbol
V
CC
I
OH
,I
OL
lclamp
ldet
Vin
Tj
Topr
Tstg
Pd
Value
30
±500
±10
±10
-0.3 to 6
150
-25 to 125
-65 to 150
0.8
Unit
V
mA
mA
mA
V
°C
°C
°C
W
Temperature Characteristics (-25°C
≤
Ta
≤
125°C)
°
°
Characteristics
Temperature Stability for Reference Voltage (V
ref
)
Temperature Stability for Multiplier Gain (K)
Symbol
∆
Vref
∆
K/∆T
Min.
-
-
Typ.
20
0.2
Max.
-
-
Unit
mV
%/°C
4
FAN7527
Electrical Characteristics
V
CC
= 14V, -25°C
≤
Ta
≤
125°C, unless otherwise stated.
Characteristics
Start Threshold Voltage
UVLO Hysteresis
< SUPPLY CURRENT SECTION >
Start-up Supply Current
Operating Supply Current
Operating Current at OVP
Dynamic Operating Supply Current
< ERROR AMPLIFIER SECTION >
Voltage Feedback Input Threshold
Line Regulation
Temperature Stability Of Vref (Note1)
Input Bias Current
Output Source Current
Output Sink Current
Output Upper Clamp Voltage (Note2)
Output Lower Clamp Voltage (Note3)
Large Signal Open Loop Gain (Note4)
Power Supply Rejection Ratio (Note5)
Unity Gain Bandwith (Note6)
Slew Rate (Note7)
< MULTIPLIER SECTION>
Input Bias Current (Pin3)
M1 Input Voltage Range (Pin3)
M2 Input Voltage Range (Pin2)
Multiplier Gain (Note8)
Maximum Multiplier Output Voltage
Temperature Stability Of K (Note9)
Ib
(m)
∆V
m
1
∆V
m
2
K
∆K/∆T
-
-
-
Vm1 = 1V, Vm2 = 3.5V
-25
≤
Ta
≤
125°C
-0.5
0
Vref
0.36
1.65
-
-
-
-
0.44
1.8
-0.2
0.5
3.8
Vref+2.5
0.52
1.95
-
uA
V
V
1/V
V
%/°C
V
ref
∆V
ref
1
∆V
ref
3
Ib
(ea)
I
source
Isink
Veao(H)
Veao(L)
G
v
PSRR
GBW
SR
Vm2 = 4V
Vm2 = 4V
Isource = 0.1mA
Isink = 0.1mA
-
14V
≤
Vcc
≤
25V
-
-
Iref =0mA, Ta =25°C
0
≤
Ta
≤
125°C
14V
≤
Vcc
≤
25V
-25
≤
Ta
≤
125°C
-
2.465
2.44
-
-
-0.5
-2
2
-
-
60
60
-
-
2.5
2.5
0.1
20
-
-4
4
6
2.25
80
80
1
0.6
2.535
2.56
10
-
0.5
-
-
-
-
-
-
-
-
V
V
mV
mV
uA
mA
mA
V
V
dB
dB
MHz
V/us
I
st
I
cc
I
cc(ovp)
I
dcc
Vcc =Vth(st) -0.2V
Output not switching
Vinv = 3V
50KHz, CI = 1nF
20
-
-
-
60
3
1.7
4
100
6
4
8
uA
mA
mA
mA
Symbol
V
th(st)
HY(st)
Test Condition
Vcc Increasing
-
Min.
10.5
2
Typ.
11.5
3
Max.
12.5
4
Unit
V
V
< UNDER VOLTAGE LOCK OUT SECTION>
Vomax(m) Vinv =0V, Vm1 = 4V
5
嵌入式系统
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