Notice – PMC Product Support Scope for Specified HDMP Part Numbers
Distribution:
This notice has been added to the front of the datasheets for the “Devices Affected” listed below.
Devices Affected:
HDMP-0421G
HDMP-0422G
HDMP-0450G
HDMP-0451G
HDMP-0452G
HDMP-0480G
HDMP-0482G
PMC-2060481* HDMP-1022G
In
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Device
Data Sheet
Device
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Th
Data Sheet
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PMC-Sierra has acquired the Fibre Channel/Storage and Gigabit Ethernet Port Bypass
Controllers and SERDES/PHY products of Agilent/Avago Technologies. This notice is to inform
customers that PMC-Sierra is supporting these devices for existing production designs only.
PMC-Sierra will only provide support for the migration of an existing design from a Pb package
to a Pb-free package. The devices are not intended for new designs and PMC-Sierra will not
provide support for new designs.
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Description:
Device
HDMP-1638G
HDMP-1646AG
r,
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07
12
Data Sheet
PMC-2060490
PMC-2060491
PMC-2060487
PMC-2060487
PMC-2060488
PMC-2060488
PMC-2060489
PMC-2060491
Customer Response
This notice is for customer information only and no customer response is required. If you have
any questions or concerns please contact your local PMC-Sierra Sales Representative listed at
this link
http://www.pmc-sierra.com/contactSales/
Do
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ad
Proprietary and Confidential to PMC-Sierra, Inc.
Document ID: PMC-2062501, Issue 1
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* Note – These data sheets have part numbers that reference Pb packaging. All part numbers
listed above are for Pb-free packaging.
Co
nt
PMC-2060486
en
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PMC-2062505* HDMP-1636AG
ea
PMC-2060485* HDMP-1536AG
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of
PMC-2060484
HDMP-1034AG
Pa
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PMC-2060483
HDMP-1032AG
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in
PMC-2060482* HDMP-1024G
er
HDMP-1646AGR1 PMC-2060491
HDMP-1687G
HDMP-T1636AG
PMC-2060493
PMC-2060491
HDMP-1636AGR1 PMC-2060491
:2
7:
Notice – PMC Product Support Scope for Specified
HDMP Part Numbers
52
AM
November 21, 2006
3
in
The HDMP-0422 is a Single Port
Bypass Circuit (PBC) with Clock
and Data Recovery (CDR)
capability included. This integrated
circuit provides a low-cost, low-
power physical-layer solution for
Fibre Channel Arbitrated Loop
(FC-AL) disk array configurations.
By using a PBC such as the HDMP-
0422, hard disks may be pulled out
or swapped while other disks in the
array are available to the system.
A PBC consists of multiple 2:1
multiplexers daisy chained along
with a CDR. Each port has two
modes of operation: “disk in loop”
and “disk bypassed.” When the
“disk in loop” mode is selected, the
loop goes into and out of the disk
drive at that port. For example,
data goes from the HDMP-0422’s
TO_NODE[n]± differential output
pins to the Disk Drive Transceiver
IC’s (e.g. an HDMP-1636A) Rx
differential input pins. Data from
the Disk Drive Transceiver IC’s Tx
differential outputs goes to the
HDMP-0422’s FM_NODE[n]±
differential input pins. Figures 2
and 3 show connection diagrams
for disk drive array applications.
tT
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the “disk in
loop” mode. HDMP-0422s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the appropriate
FM_NODE[n]± and
TO_NODE[n]± pins to
accommodate any number of hard
disks (see Figure 4). The unused
cells in the HDMP-0422 may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
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Description
When the “disk bypassed” mode is
selected, the disk drive is either
absent or non-functional and the
loop bypasses the hard disk.
Features
• Supports 1.0625 GBd Fibre
Channel operation
• Supports 1.25 GBd Gigabit
Ethernet (GE) operation
• Single PBC/CDR in one package
• CDR location determined by
choice of cable input/output
• Amplitude valid and data valid
detection (Fibre channel rate only)
on FM_NODE[0] input
• Equalizers on all inputs
• High-speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
• 0.46 W typical power at
V
CC
= 3.3 V
• 24 Pin, low-cost SSOP package
Applications
• RAID, JBOD, BTS cabinets
• One 2:1 muxes
• One 1:2 buffers
• 1
≥
N Gigabit serial buffer
• N
≥
1 Gigabit serial mux
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CAUTION:
As with all semiconductor ICs, it is advised that normal static precautionsb be taken in
the handling and assembly of this component to prevent damage and/or degradation which may be
induced by electrostatic discharge (ESD).
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An HDMP-0422 may also be used
as two 1:1 buffers, one with a CDR
and one without. For example, an
HDMP-0422 may be placed in
front of a CMOS ASIC to clean the
jitter of the outgoing signal (CDR
path) and to better read the
incoming signal (non-CDR paths).
In addition, the HDMP-0422 may
be configured as one 2:1
multiplexers or as one 1:2 buffers.
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PMC-Sierra, Inc. - Not Recommended for New Designs
07
HDMP-0422
12
:2
PMC-Sierra HDMP-0422
Single Port Bypass Circuit with CDR &
Data Valid Detection Capability
for Fibre Channel Arbitrated Loops
Data Sheet
7:
52
AM
FM_NODE[1]
FM_NODE[0]
TO_NODE[1]
TO_NODE[0]
BYPASS[1]–
EQU
BLL
TTL
BLL
EQU
1
0
1
0
DV
CPLL
AV
TTL
TTL
TTL
FM_NODE[0]_DV
Do
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CDR
The Clock and Data Recovery
(CDR) block is responsible for
frequency and phase locking onto
the incoming serial data stream
and resampling the incoming data
based on the recovered clock. An
automatic locking feature allows
the CDR to lock onto the input
data stream without external
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The HDMP-0422 design allows for
CDR placement at any location
with respect to a hard disk slot.
For example, if hard disk A is
connected to PBC cell 1, while
BYPASS[0]- is left to float high
(see Figure 2), the CDR function
will be performed before entering
the hard disk at slot A. To obtain a
CDR function after slot A (see
Figure 3), connect hard disk A to
PBC cell 0, while floating
BYPASS[1]- high. Refer to Table 1
for both pin connections.
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Figure 1. Block diagram of HDMP-0422.
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FM_NODE[0]_AV
BYPASS[0]–
MODE_DV
REFCLK
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TTL
TTL
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training controls. It does this by
continually frequency locking
onto the 106.25 MHz reference
clock (REFCLK) and then phase
locking onto the input data
stream. Once bit locked, the CDR
generates a high-speed sampling
clock. This clock is used to
sample or repeat the incoming
data to produce the CDR output.
The CDR jitter specifications
listed in this data sheet assume
an input that has been 8B/10B
encoded. The CDR will also lock
onto data encoded using other
algorithms as long as there is DC
balance and a sufficient number
of transitions.
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REFCLK INPUT
The LVTTL REFCLK input
provides a reference oscillator for
frequency acquisition of the CDR.
The REFCLK frequency should be
within
±
100 ppm of one-tenth of
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PMC-Sierra, Inc. - Not Recommended for New Designs
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be
the incoming data rate in baud
(106.25 MHz
±
100 ppm for FC-
AL running at 1.0625 GBd).
BLL OUTPUT
All TO_NODE[n]± high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0422 are
of equal strength and can drive
lengthy FR-4 PCB trace.
Unused outputs should not be left
unconnected. Ideally, unused
outputs should have their
differential pins shorted together
with a short PCB trace. If longer
traces or transmission lines are
connected to the output pins, the
lines should be differentially
terminated with an appropriate
r,
1
CDR
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0
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12
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7:
52
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FM_NODE[0]_DV OUTPUT
The Data Valid (DV) block detects
if the incoming data at
FM_NODE[0]± is valid Fibre
Channel data. The DV block checks
for sufficient K28.5+ characters
(per Fibre Channel framing rules)
and for run length violations (per
8B/10B encoding) on the data
coming out of the CDR.
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BYPASS[n]- INPUT
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0422. All BYPASS pins are
LVTTL and contain internal pull-up
circuitry. To bypass a port, the
appropriate BYPASS[n]- pin should
be connected to GND through a 1
kΩ resistor. Otherwise, the
BYPASS[n]- inputs should be left to
float, as the internal pull-up
circuitry will force them high.
MODE_DV INPUT
The active high Data Valid Mode
input selects Fibre Channel data
checking of the FM_NODE[0]±
inputs. This is accomplished by
having MODE_DV override the
BYPASS[0]- control (see Figure 1),
thereby forcing the data into the
CDR to come from the
FM_NODE[0]± inputs. The
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Table 1. Pin Connection Diagram to Achieve Desired CDR Location
(see Figures 2, 3)
Hard Disks
Connection to PBC cells
CDR position (x)
Cell connected to Cable
A
1
xA
0
A
0
Ax
1
Do
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The FM_NODE[0]_DV output is
pulled low if a run length violation
(RLV) occurs, or if there are no
commas detected (NCD) over a
specific time interval. It is pulled
high if no errors are detected.
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x denotes CDR position with respect to hard disks.
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PMC-Sierra, Inc. - Not Recommended for New Designs
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EQU INPUT
All FM_NODE[n]± high-speed
differential inputs have an
Equalization (EQU) buffer to offset
the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs. The
value of the termination resistor
should match the PCB trace
differential impedance.
Alternatively, instead of a single
resistor, two resistors in series,
with an AC ground between them,
can be connected differentially
across the FM_NODE[n]± inputs.
The latter configuration attenuates
high-frequency common mode
noise.
Any RLV and NCD errors are
stored during the 2
15
bit interval.
The FM_NODE[0]_DV output is
pulled low at the start of the 2
15
bit
interval after errors are detected.
Once low, FM_NODE[0]_DV
remains in that state until an entire
2
15
bit interval has no RLV or NCD
errors. At the start of the 2
15
bit
interval subsequent to no RLV or
NCD errors being detected,
FM_NODE[0]_DV is pulled high.
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When MODE_DV is high, the user
is able to use the BYPASS[0]- input
to bypass invalid Fibre Channel
data from the rest of the loop. For
example, if FM_NODE[0]_DV is
connected to the BYPASS[0]-
input, data from the CDR will only
be routed to TO_NODE[1]± if the
data has no RLV or NCD errors. If
the DV block detects errors, the
signal at TO_NODE[0]± will be
routed to the TO_NODE[1]±
outputs (see Figure 5).
FM_NODE[0]_AV OUTPUT
The Amplitude Valid (AV) block
detects if the incoming data on
FM_NODE[0]± is valid by
examining the differential
amplitude of that input. The
incoming data is considered valid,
and FM_NODE[0]_AV is driven
high, as long as the amplitude is
greater than 400 mV (differential
peak-to-peak). FM_NODE[0]_AV is
driven low as long as the amplitude
of the input signal is less than 100
mV (differential peak-to-peak).
When the amplitude of the input
signal is between 100-400 mV
(differential peak-to-peak), the
FM_NODE[0]_AV output is
undefined.
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7:
52
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resistor. The value of the
termination resistor should match
the PCB trace differential
impedance.
A RLV error is defined as any
consecutive sequence of 1s or 0s
greater than five in the serial bit
stream. An NCD error indicates the
absence of the seven-bit pattern
(0011111) present in the positive
disparity comma (K28.5+)
character. A K28.5+ character
should occur at the beginning of
every Fibre Channel frame of 2148
bytes (or 21480 serial bits), as well
as many times within and between
frames. If this seven-bit pattern is
not found within a 215 bit
(~31
μs)
interval, an NCD error is
generated. A counter within the
chip tracks the 2
15
bit intervals.
MODE_DV pin is an LVTTL input
and contains internal pull-up
circuitry. To select Data Valid
Mode, float MODE_DV high.
Otherwise, MODE_DV should be
connected to GND through a
1 kΩ resistor.
Do
wn
TTL
Figure 2. Connection diagram for CDR at first cell.
4
MODE_DV = LOW
1
0
BLL
lo
TO_NODE[1]
SERDES
EQU
ad
DV
TTL
ed
FM_NODE[0]_DV
FM_NODE[1]
BYPASS[1]–
0
1
[c
o
TTL
nt
by
CPLL
HARD DISK A
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CDR
BLL
lle
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TTL
en
REFCLK
EQU
tT
0
1
TO_NODE[0] = TO_LOOP
FM_NODE[0] = FM_LOOP
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BYPASS[0]– = HIGH (FLOAT)
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TTL
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TTL
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DV
TTL
FM_NODE[0]_AV
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In
1
MODE_DV = LOW
0
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BLL
,2
CPLL
TO_NODE[1] = TO_LOOP
EQU
TTL
TTL
FM_NODE[0]_DV
7D
CDR
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FM_NODE[1] = FM_LOOP
1
em
be
0
REFCLK
TTL
r,
BYPASS[1]– = HIGH (FLOAT)
PMC-Sierra, Inc. - Not Recommended for New Designs
20
BLL
Figure 3. Connection diagram for CDR at last cell.
TTL
07
EQU
TO_NODE[0]
SERDES
HARD DISK A
0
1
12
FM_NODE[0]
:2
7:
5
BYPASS[0]–
2
AM
AV
TTL
FM_NODE[0]_AV
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