GS8673ET36BHK-550I
260-Ball BGA
Industrial Temp
Features
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaDDR-IIIe™ Interface
• Common I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35 V nominal V
DD
• 1.2 V JESD8-16A BIC-3 Compliant Interface
• 1.5 V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–HK: 5/6 RoHS-compliant package (leaded package balls,
lead-free die bumps)
72Mb SigmaDDR-IIIe™
Burst of 2 ECCRAM™
Clocking and Addressing Schemes
550 MHz
1.35 V V
DD
1.2 V to 1.5 V V
DDQ
The GS8673ET36BHK SigmaDDR-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used solely to control the
data input registers. Consequently, data input setup and hold
windows can be optimized independently of address and
control input setup and hold windows.
Each internal read and write operation in a SigmaDDR-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 4M x 18 has
2M addressable index).
SigmaDDR-IIIe™ Family Overview
The SigmaDDR-IIIe family of SRAMs are the Common I/O
half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high
performance SRAMs. Although very similar to GSI's second
generation of networking SRAMs, the SigmaQuad-II/
SigmaDDR-II family, this third generation family of SRAMs
offers new features that allow much higher speeds, such as
user-configurable on-die input termination, improved output
signal integrity, and adjustable pipeline length.
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Parameter Synopsis
Speed Bin
-550
Operating Frequency
550 / 375 MHz
Data Rate (per pin)
1100 / 750 Mbps
Read Latency
3.0 / 2.0
V
DD
1.25V to 1.4V
Rev: 1.00 8/2019
1/36
© 2019, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8673ET36BHK-550I
2M x 36 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
DQ26
V
SS
DQ25
V
SS
DQ24
DQ23
V
SS
CQ1
CQ1
V
SS
DQ30
DQ29
V
SS
DQ28
V
SS
DQ27
V
SS
V
DD
2
V
DDQ
DQ35
V
DDQ
DQ34
V
DDQ
DQ33
DQ32
V
DDQ
DQ31
V
DDQ
V
SS
DQ22
V
DDQ
DQ21
DQ20
V
DDQ
DQ19
V
DDQ
DQ18
V
DDQ
3
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD1
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
4
V
DDQ
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
V
DDQ
5
MCL
MVQ
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD1
KD1
V
SS
DLL
V
SS
MCH
V
SS
NU
I
V
SS
TCK
TDO
6
MCL
(CFG)
7
MCL
NC
(RSVD))
8
ZQ
MCL
(SIOM)
9
PZT1
PZT0
V
SS
NC
(144 Mb)
10
V
DDQ
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
V
DDQ
11
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD0
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
12
V
DDQ
DQ0
V
DDQ
DQ1
V
DDQ
DQ2
DQ3
V
DDQ
DQ4
V
DDQ
V
SS
DQ13
V
DDQ
DQ14
DQ15
V
DDQ
DQ16
V
DDQ
DQ17
V
DDQ
13
V
DD
V
SS
DQ9
V
SS
DQ10
V
SS
DQ11
DQ12
V
SS
CQ0
CQ0
V
SS
DQ5
DQ6
V
SS
DQ7
V
SS
DQ8
V
SS
V
DD
MCL
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
NU
I
(x18)
V
DD
NC
(288 Mb)
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
(B2)
V
SS
V
DDQ
MZT1
R/W
V
SS
CK
CK
V
SS
LD
MZT0
V
DDQ
V
SS
AZT1
V
DD
NC
(RSVD)
V
SS
SA
V
SS
SA
V
SS
KD0
KD0
V
SS
MCH
V
SS
RST
V
SS
NU
I
V
SS
TMS
TDI
RLM0
ZT
MCL
MCL
RLM1
Notes:
1. Pins 5A, 7A, and 6B are reserved for future use. They must be tied Low.
2. Pins 9N and 5R are reserved for future use. They must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 9D is reserved as address pin SA for 144Mb devices. It is a true no-connect in this device.
8. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.
9. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
10. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.
11. Pins 7B and 7W are reserved for future use. They are true no-connects in this device.
Rev: 1.00 8/2019
2/36
© 2019, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8673ET36BHK-550I
Pin Description
Symbol
SA
Description
Address—Read
or Write Address is registered on
CK
Write/Read Data—Registered
on
KD
and
KD
during Write operations. Driven by
CK
and
CK,
and
synchronized with
CQ
and
CQ
during Read operations.
DQ[17:0]
DQ[35:18]
Read Data Valid—Driven
high one half cycle before valid Read Data.
Primary Input Clocks—Dual
single-ended. For Address and Control input latching, internal timing control,
and Read Data and Echo Clock output timing control.
Write Data Input Clocks—Dual
single-ended. For Write Data input latching.
KD0, KD0—latch Write Data (DQ[17:0] in x36).
KD1, KD1—latch Write Data (DQ[35:18] in x36).
Echo Clocks—Free
running source synchronous output clocks.
Load Enable—Registered
onCK.
LD = 0: Loads a new address and initiates a Read or Write operation.
LD = 1: Initiates a NOP operation.
Read / Write Enable—Registered
on
CK.
R/W = 0: initiates a Write operation when LD = 0.
R/W = 1: initiates a Read operation when LD = 0.
Address Input Termination Pull-Up Enable—Registered
onCK.
AZT1 = 0: enables termination pull-up on Address (SA)
AZT1 = 1: disables termination pull-up on Address (SA)
DLL Enable—Weakly
pulled High internally.
DLL = 0: disables internal DLL.
DLL = 1: enables internal DLL.
Reset—Holds
the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Read Latency Select 1:0—Must
be tied High or Low.
RLM[1:0] = 00: reserved.
RLM[1:0] = 01: selects 2.0 cycle Read Latency.
RLM[1:0] = 10: selects 3.0 cycle Read Latency.
RLM[1:0] = 11: reserved.
Output Driver Impedance Control Resistor Input—Must
be connected to V
SS
through an external
resistor RQ to program output driver impedance.
Input Termination Impedance Control Resistor Input—Must
be connected to V
SS
through an external
resistor RT to program input termination impedance.
Type
Input
DQ[35:0]
I/O
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
CQ[1:0],
CQ[1:0]
LD
Output
Input
Input
Output
Input
R/W
Input
AZT1
Input
DLL
Input
RST
Input
RLM[1:0]
Input
ZQ
ZT
Input
Input
Rev: 1.00 8/2019
3/36
© 2019, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8673ET36BHK-550I
Pin Description (Continued)
Symbol
Description
Input Termination Mode Select—Selects
the termination mode used for all terminated inputs. Must be tied
High or Low.
MZT[1:0] = 00: disabled.
MZT[1:0] = 01: RT/2 Thevenin-equivalent (pull-up = RT, pull-down = RT).
MZT[1:0] = 10: RT Thevenin-equivalent (pull-up = 2*RT, pull-down = 2*RT).
MZT[1:0] = 11: reserved.
Input Termination Configuration Select—Selects
which inputs are terminated. Must be tied High or Low.
PZT[1:0] = 00: Write Data only.
PZT[1:0] = 01: Write Data, Input Clocks.
PZT[1:0] = 10: Write Data, Address, Control.
PZT[1:0] = 11: Write Data, Address, Control, Input Clocks.
I/O Voltage Select—Indicates
what voltage is supplied to the V
DDQ
pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2 V to 1.35 V nominal V
DDQ
.
MVQ = 1: Configure for 1.5 V nominal V
DDQ
.
Core Power Supply—1.35
V nominal core supply voltage.
I/O Power Supply—1.2
V to 1.5 V nominal I/O supply voltage. Configured via MVQ pin.
Input Reference Voltage—Input
buffer reference voltage.
Ground
JTAG Clock
JTAG Mode Select—Weakly
pulled High internally.
JTAG Data Input—Weakly
pulled High internally.
JTAG Data Output
Must Connect High—May
be tied to V
DDQ
directly or via a 1k resistor.
Must Connect Low—May
be tied to V
SS
directly or via a 1k resistor.
No Connect—There
is no internal chip connection to these pins. They may be left unconnected, or tied High
or Low.
Not Used, Input—There
is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied Low. They should not be tied
High.
Not Used Input/Output—There
is an internal chip connection to these I/O pins, but they are unused by the
device. The drivers are tri-stated internally. They are pulled Low internally. They may be left unconnected or
tied Low. They should not be tied High.
Type
MZT[1:0]
Input
PZT[1:0]
Input
MVQ
Input
V
DD
V
DDQ
V
REF
V
SS
TCK
TMS
TDI
TDO
MCH
MCL
NC
—
—
—
—
Input
Input
Input
Output
Input
Input
—
NU
I
Input
NU
IO
I/O
Rev: 1.00 8/2019
4/36
© 2019, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8673ET36BHK-550I
On-Chip Error Correction
SigmaDDR-IIIe ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on
each DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on DQ[8:0], DQ[17:9],
DQ[26:18], or DQ[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible
to the user).
The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a
single SER event very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit”
represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of
multi-bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb (measured at sea level)).
Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”, in any 9-bit
“data byte”) for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such
error-bit allocation is unnecessary with ECCRAMs the entire memory array can be utilized for data storage, effectively providing
12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC.
Functional Description
Common I/O ECCRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-IIIe ECCRAM interface and truth table are optimized for burst reads and writes. Common I/O
ECCRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high
speed Common I/O ECCRAM data bandwidth in half. Applications of this sort are better served by Separate I/O ECCRAMs such
as the SigmaQuad-IIIe series.
Rev: 1.00 8/2019
5/36
© 2019, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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