low-power, first-in first-out (FIFO) memories with clocked read
and write interfaces. All are 18 bits wide. The CY7C455 has a
512-word memory array, the CY7C456 has a 1,024-word
memory array, and the CY7C457 has a 2,048-word memory
array. The CY7C455, CY7C456, and CY7C457 can be cas-
caded to increase FIFO depth. Programmable features include
Almost Full/Empty flags and generation/checking of parity.
These FIFOs provide solutions for a wide variety of data buff-
ering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW).
Logic Block Diagram
D
0 – 17
Pin Configurations
PLCC
Top View
V
CC
V
CC
(N)
D
3
D
4
D
5
D
6
D
7
D
8
V
SS
D
9
D
10
D
11
D
12
INPUT
REGISTER
CKW
ENW
PARITY
WRITE
CONTROL
FLAG/PARITY
PROGRAM
REGISTER
7 6 5 4 3 2 1 52 51 50 49 48 47
8
9
10
XI 11
HF
ENW 12
E/F
CKW 13
PAFE/XO
HF 14
E/F 15
XO/PAFE 16
Q
0
17
Q
1
18
Q
2
19
Q
3
20
Q
4
Q
5
Q
6
Q
7
Q
8
/PG1/PE1
V
SS
D
2
D
1
D
0
46
45
44
43
42
41
40
39
38
37
36
35
34
29 30 31 32 33
Q
11
Q
12
Q
13
Q
14
c455-2
D
13
D
14
D
15
D
16
D
17
FL/RT
MR
CKR
ENR
OE
Q
17
/PG2/PE2
Q
16
Q
15
FLAG
LOGIC
RAM
ARRAY
512 x 18
1024 x 18
2048 x 18
7C455
7C456
7C457
WRITE
POINTER
MR
FL/RT
XI
RESET
LOGIC
READ
POINTER
21 22 23 24 25 26 27 28
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
OE
Q
0 – 7
, Q
8
/PG1/PE1
Q
9– 16
, Q17/PG2/PE2
READ
CONTROL
RETRANSMIT
LOGIC
CKR
ENR
c455-1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
October 1992 - Revised January 3, 1997
V
SS
(N)
Q
9
Q
10
CY7C455
CY7C456
CY7C457
Pin Configurations
(continued)
PQFP
Top View
D
4
D
5
D
6
D
7
D
8
V
SS
V
CC
V
CC
(N)
D
9
D
10
D
11
D
12
D
3
Functional Description
(continued)
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit the
data. Read enable (ENR) and the write enable (ENW) must
both be HIGH during the retransmit, and then ENR is used to
access the data.When ENW is asserted, data is written into
the FIFO on the rising edge of the CKW signal. While ENW is
held active, data is continually written into the FIFO on each
CKW cycle. The output port is controlled in a similar manner
by a free-running read clock (CKR) and a read enable pin
(ENR). In addition, the CY7C455, CY7C456, and CY7C457
have an output enable pin (OE). The read (CKR) and write
(CKW) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 83.3 MHz are
achievable in the standalone configuration, and up to 83.3
MHz is achievable when FIFOs are cascaded for depth expan-
sion.
Depth expansion is possible using the cascade input (XI), cas-
cade output (XO), and First Load (FL) pins. The XO pin is
connected to the XI pin of the next device, and the XO pin of
the last device should be connected to the XI pin of the first
device. The FL pin of the first device is tied to V
SS
.
The CY7C455, CY7C456, and CY7C457 provide three status
pins. These pins are decoded to determine one of six states:
Empty, Almost Empty, Less than or Equal to Half Full, Greater
than Half Full, Almost Full, and Full (see
Table 1).
The Almost
Empty/Full flag (PAFE) shares the XO pin on the CY7C455,
CY7C456, and CY7C457. This flag is valid in the standalone
and width-expansion configurations. In the depth expansion,
this pin provides the expansion out (XO) information that is
used to signal the next FIFO when it will be activated.
The flags are synchronous, i.e., they change state relative to
either the read clock (CKR) or the write clock (CKW). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the CKR. The flags denoting
Half Full, Almost Full, and Full states are updated exclusively
by CKW. The synchronous flag architecture guarantees that
the flags maintain their status for some minimum time. This
time is typically equal to approximately one cycle time.
The CY7C455/6/7 uses center power and ground for reduced
noise. All configurations are fabricated using an advanced
0.65u CMOS technology. Input ESD protection is greater
than 2001V, and latch-up is prevented by the use of guard
rings.
52 51 50 49 48 47 46 45 44 43 42 41 40
D
2
D
1
D
0
XI
ENW
CKW
HF
E/F
XO/PAFE
Q
0
Q
1
Q
2
Q
3
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
7C455
33
7C456
7C457
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
D
13
D
14
D
15
D
16
D
17
FL/RT
MR
CKR
ENR
OE
Q
17
/PG2/PE2
Q
16
Q
15
c455-3
Q
4
Q
5
Q
6
Q
7
Q
8
/PG1/PE1
V
SS
V
SS
(N)
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
2
CY7C455
CY7C456
CY7C457
Selection Guide
7C455/6/7–12
Maximum Frequency (MHz)
Maximum Cascadable Frequency
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Clock HIGH Time (ns)
Minimum Clock LOW Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Maximum Current
(mA)
Commercial
Industrial
83.3
83.3
9
12
5
5
4
0
9
160
180
7C455/6/7–14
71.4
71.4
10
14
6.5
6.5
5
0
10
160
180
7C455/6/7–20
50
50
15
20
9
9
6
0
15
140
160
7C455/6/7–30
33.3
33.3
20
30
12
12
7
0
20
120
140
Selection Guide
(continued)
CY7C455
Density
OE, Depth Cascadable
Package
512 x 18
Yes
52-Pin PLCC/PQFP
CY7C456
1,024 x 18
Yes
52-Pin PLCC/PQFP
CY7C457
2,048 x 18
Yes
52-Pin PLCC/PQFP
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied ............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
[1]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Note:
1. T
A
is the “instant on” case temperature.
3
CY7C455
CY7C456
CY7C457
Pin Definitions
Signal Name
D
0
−
17
I/O
I
Description
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D
0
−
17
) into
the FIFO’s memory. If MR is asserted at the rising edge of CKW, data is written into the FIFO’s
programming register. D
8
,
17
are ignored if the device is configured for parity generation.
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q
0
−
7
,
Q
9
−
16
) out of the FIFO’s memory. If MR is active at the rising edge of CKR, data is read from the
programming register.
Function varies according to mode:
Parity disabled – same function as Q
0
−
7
and Q
9
−
16
Parity enabled, generation – parity generation bit (PG
x
)
Parity enabled, check – Parity Error Flag (PE
x
)
Enable Write: Enables the CKW input (for both non-program and program modes).
Enable Read: Enables the CKR input (for both non-program and program modes).
Write Clock: The rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost
Full, and Full flag states. When MR is asserted, CKW writes data into the program register.
Read Clock: The rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and
Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.
Half Full Flag: Synchronized to CKW.
Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW.
Dual-Mode Pin:
Not Cascaded – programmable Almost Full is synchronized to CKW; Programmable Almost Empty is
synchronized to CKR.
Cascaded – expansion out signal, connected to XI of next device.
Expansion-In Pin:
Not Cascaded – XI is tied to V
SS
.
Cascaded – expansion Input, connected to XO of previous device.
First Load/Retransmit Pin:
Cascaded – the first device in the daisy chain will have FL tied to V
SS
; all other devices will have FL tied
to V
CC
(Figure
1).
Not Cascaded – tied to V
CC
.
Retransmit function is also available in standalone mode by strobing RT.
Master Reset: Resets device to empty condition.
Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at
16 or less locations from Full/Empty.
Programming Mode: Data present on D
0 - 9,10, or 11
and D
15-17
is written into the programmable register
on the rising edge of CKW. Program register contents appear on Q
0 - 9,10, or 11
and Q
15-17
after the rising
edge of CKR.
Output Enable for Q
0
−
7
, Q
9
−
16
, Q
8
/PG1/PE1 and Q
17
/PG2/PE2 pins.
Q
0
−
7
Q
9
−
16
Q
8
/PG1/PE1
Q
17
/PG2/PE2
O
O
ENW
ENR
CKW
CKR
HF
E/F
PAFE/XO
I
I
I
I
O
O
O
XI
I
FL/RT
I
MR
I
OE
I
4
CY7C455
CY7C456
CY7C457
Electrical Characteristics
Over the Operating Range
7C455/6/7–
12
Parameter
V
OH
V
OL
V
IH[2]
V
IL[2]
I
IX
I
OS[3]
I
OZL
I
OZH
I
CC1[4]
I
CC2[5]
I
SB[6]
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Short
Circuit Current
Output OFF, High Z
Current
Operating Current
Operating Current
Standby Current
V
CC
= Max.
V
CC
= Max., V
OUT
= GND
OE > V
IH
, V
SS
< V
O
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
Com’l
Ind
Com’l
Ind
Com’l
Ind
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–10
–90
–10
+10
160
180
90
100
40
40
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
–10
+10
160
180
90
100
40
40
Max
7C455/6/7– 7C455/6/7– 7C455/6/7–
14
20
30
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
–10
+10
140
160
90
100
40
40
Max
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
–10
+10
120
140
90
100
40
40
Max
Min.
2.4
0.4
V
CC
0.8
+10
Max
Unit
V
V
V
V
µA
mA
µA
mA
mA
mA
mA
mA
mA
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
12
Unit
pF
pF
AC Test Loads and Waveforms
[8, 9, 10, 11, 12]
R1 500Ω
5V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
200Ω
OUTPUT
R2
333Ω
3.0V
GND
≤
3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤
3 ns
c455-5
c455-4
2V
Notes:
2. The V
IH
and V
IL
specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or V
SS
.
3. Test no more than one output at a time for not more than one second.
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (f
MAX
), while data inputs
switch at f
MAX
/2. Outputs are unloaded.
5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
6. All input signals are connected to V
CC
. All outputs are unloaded. Read and write clocks switch at maximum frequency (f
MAX
).
7. Tested initially and after any design or process changes that may affect these parameters.
8. C
L
= 30 pF for all AC parameters except for t
OHZ
.
9. C
L
= 5 pF for t
OHZ
.
10. All AC measurements are referenced to 1.5V except t
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