BU-65178/65179*/61588/61688*/61689*
MINIATURE ADVANCED
COMMUNICATION ENGINE
(MINI-ACE®) AND MINI-ACE PLUS*
Make sure the next
Card you purchase
has...
TM
®
FEATURES
•
5 Volt Only
•
Fully Integrated MIL-STD-1553 A/B
STANAG 3838 Compliant Terminals
•
One-Square-Inch Package
•
Smallest BC/RT/MT In The Industry
•
Hardware and Software Compatible
with BU-61580 ACE Series
•
Flexible Processor/Memory Interface
•
Bootable RT* Option
•
4K x 16 or 64K x 16* Shared RAM
•
Automatic BC Retries
•
Programmable BC Gap Times
DESCRIPTION
The BU-61588 Mini-ACE and BU-61688 Mini-ACE Plus* integrates two
5-volt-only transceivers, protocol, memory management, processor interface
logic, and 4K x 16, or 64K x 16* words of RAM in a choice of pin grid array
(PGA), quad flat pack or gull lead packages. The Mini-ACE is packaged in a
1.0 square inch, low profile, cofired ceramic multi-chip-module (MCM) pack-
age making it the smallest integrated MIL-STD-1553 BC/RT/MT in the indus-
try.
The Mini-ACE provides full compatibility to DDC’s BU-61580 and BU-65170
Advanced Communication Engine (ACE). As such, the Mini-ACE includes all
the hardware and software architectural features of the ACE.
The Mini-ACE contains internal address latches and bidirectional data buffers
to provide a direct interface to a host processor bus. The memory manage-
ment scheme for RT mode provides three data structures for buffering data.
These structures, combined with the Mini-ACE’s extensive interrupt capabil-
ity, serve to ensure data consistency while off-loading the host processor.
The Mini-ACE Plus* can optionally boot-up as a RT with the Busy bit set for
1760 applications. The Mini-ACE BC mode implements several features
aimed at providing an efficient real-time software interface to the host proces-
sor including automatic retries, programmable intermessage gap times, auto-
matic frame repetition, and flexible interrupt generation.
The advanced architectural features of the Mini-ACE, combined with its small
size and high reliability, make it an ideal choice for demanding military and indus-
trial processor-to-1553 applications.
•
Programmable Illegalization
•
Simultaneous RT/Monitor Mode
•
Operates From 10*/12 /16 / 20* MHz
Clock
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7677 or 7381
7771
All trademarks are the property of their respective owners.
©
1998, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
4K X 16
OR
64K X 16
SHARED
RAM
TX/RX_A
*
CH. A
TRANSCEIVER
A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS BUS
ADDRESS
BUFFERS
TX/RX_A
DATA
BUFFERS
D15-D0
PROCESSOR
DATA BUS
TX/RX_B
A15-A0
PROCESSOR
ADDRESS BUS
2
TRANSCEIVER
B
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RTAD4-RTAD0, RTADP
CLK_IN,
MSTCLR,SSFLAG/EXT_TRG
CH. B
TX/RX_B
RT ADDRESS
RT_AD_LAT
MISCELLANEOUS
BU-65178/65179*/61688*/61689*
V-1/13-0
FIGURE 1. BU-65178/65179*/61588/61688*/61689*
TABLE 1. BU-65178/65179*/61588/61688*/61689* SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
Logic +5 V
Transceiver +5 V (Note 12)
Logic
Voltage Input Range
MIL-STD-1553 Transceiver Signals
Powered Input Range (Note 14)
Unpowered Input Range
RECEIVER
Differential Input Resistance (Notes 1-7)
Differential Input Capacitance (Notes 1-7)
Threshold Voltage, Transformer Coupled, Measured on Stub
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
Direct Coupled Across 35
Ω,
Measured on Bus
Transformer Coupled Across 70
Ω,
Measured on Bus:
• Standard Product = – XX0
• 1760 Amplitude Compliant Product = – XX2
( Note 13 and Ordering Information – Test Criteria)
Output Noise, Differential (Direct Coupled)
Output Offset Voltage, Transformer Coupled Across 70 ohms
Rise/Fall Time
LOGIC
VIH
VIL
IIH (Vcc = 5.5 V, VIN = Vcc)
IIH (Vcc = 5.5 V, VIN = 2.7 V)
SSFLAG/EXT_TRIG
All Other Inputs
IIL (Vcc = 5.5 V, VIN = 0.4 V)
SSFLAG/EXT_TRIG
All Other Inputs
VOH (Vcc = 4.5 V, VIH = 2.7 V, VIL = 0.2 V, IOH = max)
VOL (Vcc = 4.5 V, VIH = 2.7 V, VIL = 0.2 V, IOL = max)
IOL
DB15-DB0
A15-A0
MEMOE/ADDR_LAT
MEMWR/ZEROWAIT
DTREQ/16/8
DTACK/POLARITY_SEL
INT
READYD
IOEN
IOH
DB15-DB0
A15-A0
MEMOE/ADDR_LAT
MEMWR/ZEROWAIT
DTREQ/16/8
DTACK/POLARITY_SEL
INT
READYD
IOEN
CI (Input Capacitance)
CIO (Bi-directional signal input capacitance)
MIN
TYP
MAX
UNITS
-0.3
-0.3
-0.3
-5V_XCVR - 0.3
-1.5
2.5
0.200
6.0
7.0
Vcc+0.3
5V_XCVR + 0.3
+1.5
V
V
V
V
V
kohm
pF
Vp-p
Vpeak
5
0.860
10
6
18
20
-250
100
2.0
-10
-692
-346
-794
-397
2.4
6.4
7
21
22
150
9
27
27
10
250
300
Vp-p
Vp-p
Vp-p
mVp-p, diff
mV
nsec
V
V
µA
µA
µA
µA
µA
V
V
mA
0.8
10
-84
-42
-100
-50
0.4
3.2
mA
-6.4
mA
-3.2
50
50
mA
pF
pF
Data Device Corporation
www.ddc-web.com
3
BU-65178/65179*/61688*/61689*
V-1/13-0
TABLE 1. BU-65178/65179*/61588/61688*/61689* SPECIFICATIONS (CONT.)
PARAMETER
1553 MESSAGE TIMING
Completion of CPU Write (BC Start)- to-Start of Next Message
BC Intermessage Gap (Note 8)
BC/RT/MT Response Timeout (Note 9)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
T Response Time (Note 11)
Transmitter Watchdog Timeout
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
BU-65178/61588X3
• +5 V (Logic)
• +5 V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
BU-65178/65179/61588X0
• +5 V (Logic)
BU-65178/65179/61588X3
• +5 V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61688*/61689X0*
• +5 V (Logic)
BU-61688*/61689X3*
• +5 V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER DISSIPATION
Total Hybrid
BU-65178/65179/61588X0
• +5 V (Logic)
BU-65178/61588/65179X3
• Idle
• 25% Duty Cycle
• 50% Duty Cycle
• 100% Duty Cycle
BU-61688*/61689X0*
• +5 V (Logic)
BU-61688*/61689X3*
• Idle
• 25% Duty Cycle
• 50% Duty Cycle
• 100% Duty Cycle
Hottest Die
BU-65178/61588X3/65179X3*/ BU-61688*/61689X3*
• Idle
• 25% Duty Cycle
• 50% Duty Cycle
• 100% Duty Cycle
MIN
TYP
2.5
9.5
17.5
21.5
49.5
127
4
18.5
22.5
50.5
129.5
668
19.5
23.5
51.5
131
7
MAX
UNITS
µs
µs
µs
µs
µs
µs
µs
µs
4.5
4.75
5.0
5.0
23
116
222
328
540
46
116
217
318
519
5.5
5.25
100
160
265
370
580
200
180
285
390
600
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.115
0.64
0.93
1.22
1.81
0.230
0.64
0.93
1.22
1.80
0.18
0.42
0.66
1.14
0.5
0.88
1.11
1.33
1.97
1.0
0.99
1.22
1.45
1.90
0.28
0.51
0.75
1.22
W
W
W
W
W
W
W
W
W
W
W
W
W
W
*
Mini-ACE PLUS with 64K Words of RAM. RAM impact to Power Supply is based on Host Processor activity; subtract 140 mA if Host is idle.
Data Device Corporation
www.ddc-web.com
4
BU-65178/65179*/61688*/61689*
V-1/13-0
TABLE 1. BU-65178/65179*/61588/61688*/61689* SPECIFICATIONS (CONT.)
PARAMETER
Frequency
BU-61588/61688*/65178
• Default Mode
• Software Programmable Option
BU-61689*
• Default Mode
• Software Programmable Option
BU-65179*
• Pin Programmable Option
Long Term Tolerance
MIN
TYP
MAX
UNITS
16
12
20
10
10/12/16/20
MHz
MHz
MHz
MHz
MHz
• 1553A Mode
• 1553B Mode
Short Term Tolerance, 1 second
• 1553A Mode
• 1553B Mode
Duty Cycle
• 16 MHz
• 12 MHz
• 10 MHz*
• 20 MHz
THERMAL
Thermal Resistance, Junction-to-Case, Hottest Die (θJC)
BU-65178/61588X3*
Operating Case/Ball Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
-EXX
Storage Temperature
Lead Temperature (soldering, 10 sec.)
0.01
0.1
0.001
0.01
33
40
40
40
67
60
60
60
%
%
%
%
%
%
%
%
6.8
-55
-40
0
-40
-65
+125
+85
+70
+100
+150
+300
°C/W
°C
°C
°C
°C
°C
°C
PHYSICAL CHARACTERISTICS
Size
BU-65178/61588 P
BU-65179*/61688*/61689*
BU-65178/61588 F/G
BU-65179*/61688*/61689*
Weight
BU-65178/61588 F/P/G
BU-65179*/61688*/61689*
1.0 X 1.0 X 0.150
(25.4 x 25.4 x 3.81)
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
0.3
(9)
in.
(mm)
in.
(mm)
oz
(g)
Data Device Corporation
www.ddc-web.com
5
BU-65178/65179*/61688*/61689*
V-1/13-0
FPGA/CPLD
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