Integrated Device Technology, Inc.
FAST CMOS
18-BIT UNIVERSAL BUS
TRANSCEIVER
WITH 3-STATE OUTPUTS
IDT74FCT16601AT/CT/ET
IDT74FCT162601AT/CT/ET
PRODUCT PREVIEW
bit registered transceivers are built using advanced dual metal
CMOS technology. These high-speed, low-power 18-bit reg-
• Common features:
istered bus transceivers combine D-type latches and D-type
– 0.5 MICRON CMOS Technology
flip-flops to allow data flow in either direction in a transparent,
– High-speed, low-power CMOS replacement for
latched or clocked mode. Each direction has an independent
ABT functions
latch enable, an independent clock with a clock enable, and an
–
Typical t
SK
(o) (Output Skew) < 250ps
independent output enable. The package is organized with a
– Low input and output leakage
≤1µA
(max.)
flow-through signal pin organization to ease board layout. All
– ESD > 2000V per MIL-STD-883, Method 3015;
inputs are designed with hysteresis for improved noise mar-
> 200V using machine model (C = 200pF, R = 0)
gin.
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
This transceiver is ideally suited for high speed memory
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
interfaces which utilize high speed synchronous writes, by
– Extended commercial range of -40°C to +85°C
clocking the data into a high speed register. Reads can then
– V
CC
= 5V
±10%
be performed in a transparent or latched mode utilizing the
• Features for FCT16601AT/CT/ET:
same transceiver.
– High drive outputs (-32mA I
OH
, 64mA I
OL
)
The FCT16601AT/CT/ET are ideally suited for driving
– Power off disable outputs permit “live insertion”
high-capacitance loads and low-impedance backplanes. The
– Typical V
OLP
(Output Ground Bounce) < 1.0V at
output buffers are designed with power off disable capability
V
CC
= 5V, T
A
= 25°C
to allow "live insertion" of boards when used as backplane
• Features for FCT162601AT/CT/ET:
drivers.
– Balanced Output Drivers:
±24mA
The FCT162601AT/CT/ET have balanced output drive
– Reduced system switching noise
with current limiting resistors. This offers low ground bounce,
– Typical V
OLP
(Output Ground Bounce) < 0.6V at
minimal undershoot, and controlled output fall times–reducing
V
CC
= 5V,T
A
= 25°C
the need for external series terminating resistors. The
FCT162601AT/CT/ET are plug-in replacements for the
DESCRIPTION:
FCT16601AT/CT/ET and ABT16601 for on-board bus inter-
The FCT16601AT/CT/ET and FCT162601AT/CT/ET 18- face applications.
FEATURES:
P
R
E
V
E
I
W
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
1
56
55
2
28
30
P
29
27
3
R
O
D
C
U
T
A
1
CE
1D
C1
CLK
CE
1D
C1
CLK
54
B
1
3247 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
AUGUST 1996
5.9
DSC-3247/-
1
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
56
55
54
53
52
51
50
49
48
47
46
45
44
CLKENAB
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
V
TERM(2)
Terminal Voltage with Respect to –0.5 to +7.0
GND
–0.5 to
V
TERM(3)
Terminal Voltage with Respect to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
Unit
V
V
°
C
mA
3247 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
14 SO56-1 43
SO56-2
15 SO56-3 42
16
17
18
19
20
21
22
23
24
25
26
27
28
41
40
39
38
37
36
35
34
33
32
31
30
29
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
P
E
R
V
E
I
W
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max. Unit
6.0
pF
8.0
pF
3247 lnk 04
CLKBA
SSOP/
TSSOP/TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
A to B Clock Enable Input
B to A Clock Enable Input
3247 tbl 01
P
Description
R
O
CLKENBA
U
D
3247 drw 02
T
C
FUNCTION TABLE
(1,4)
CLKENAB
X
X
X
H
L
L
L
L
OEAB
H
L
L
L
L
L
L
L
Inputs
LEAB
X
H
H
L
L
L
L
L
CLKAB
X
X
X
X
↑
↑
L
H
A
X
L
H
X
L
H
X
X
Outputs
B
Z
L
H
B0
(2)
L
H
B0
(2)
B0
(3)
CLKENAB
CLKENBA
NOTES:
3247 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA
,
LEBA and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ =
LOW-to-HIGH Transition
5.9
2
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40°C to +85°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= GND
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
Min.
2.0
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–
0.7
–
140
Max.
—
Unit
V
V
µA
0.8
±1
±1
±1
±1
±1
±1
–
1.2
–
225
—
µA
V
mA
mV
µA
V
CC
= Max., V
IN
= GND or V
CC
OUTPUT DRIVE CHARACTERISTICS FOR FCT16601T
Symbol
I
O
V
OH
Parameter
Output Drive Current
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Max., V
O
= 2.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
P
R
E
V
E
I
W
—
–80
—
—
100
5
500
3247 lnk 05
Min.
–50
2.5
2.4
2.0
—
—
Typ.
(2)
—
Max.
–
180
—
—
—
0.55
Unit
mA
V
V
V
V
I
OH
= –3mA
I
OH
= –15mA
I
OH
= –32mA
(4)
3.5
3.5
3.0
0.2
—
V
OL
I
OFF
Output LOW Voltage
Input/Output Power Off Leakage
V
CC
= Min.
I
OL
= 64mA
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
≤
4.5V
OUTPUT DRIVE CHARACTERISTICS FOR FCT162601T
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
P
O
R
D
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –24mA
I
OL
= 24mA
U
T
C
±
1
µ
A
3247 lnk 06
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
3247 lnk 07
5.9
3
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
OEAB
= V
CC
OEBA
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (CLKBA)
50% Duty Cycle
OEAB
= V
CC
OEBA
= GND
LEAB = GND
CLKENBA
= GND
One Bit Toggling
f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (CLKBA)
50% Duty Cycle
OEAB
= V
CC
OEBA
= GND
LEAB = GND
CLKENBA
= GND
Eighteen Bits Toggling
f
i
= 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
0.5
75
Max.
1.5
120
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
0.8
1.7
mA
V
IN
= 3.4V
V
IN
= GND
—
1.3
3.2
V
IN
= V
CC
V
IN
= GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
P
E
R
V
IN
= 3.4V
V
IN
= GND
V
E
I
W
3.8
6.5
(5)
8.5
20.8
(5)
—
—
3247 tbl 09
P
R
O
U
D
T
C
5.9
4
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16601AT/
FCT162601AT
Symbol
Parameter
Condition
(1)
FCT16601CT/
FCT162601CT
Min.
(2)
FCT16601ET/
FCT162601ET
Min.
(2)
Max.
Unit
Min.
(2)
Max.
Max.
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
SU
t
H
t
W
CLKAB or CLKBA frequency
(4)
C
L
= 50pF
—
1.5
1.5
1.5
1.5
1.5
4.0
0
1.0
2.5
2.0
2.5
0
2.5
150
4.9
5.2
4.7
5.8
6.2
—
—
—
—
—
—
1.5
1.5
1.5
1.5
1.5
3.0
0
150
4.4
4.7
4.5
5.3
5.7
—
1.5
1.5
1.5
1.5
1.5
2.4
0
1.0
1.5
0.5
2.0
0
2.5
3.0
—
150
3.8
4.2
4.2
4.8
5.2
—
—
—
—
—
—
—
—
—
0.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3247 tbl 09
Propagation Delay
R
L
= 500Ω
Ax to Bx or Bx to Ax
Propagation Delay
LEBA to Ax, LEAB to Bx
Propagation Delay
CLKBA to Ax, CLKAB to Bx
Output Enable Time
OEBA
to Ax,
OEAB
to Bx
Output Disable Time
OEBA
to Ax,
OEAB
to Bx
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax after CLKAB, Bx after CLKBA
Set-up Time HIGH or LOW Clock LOW
Ax to LEAB, Bx to LEBA
Clock HIGH
Hold Time, HIGH or LOW
Ax after LEAB, Bx after LEBA
Set-up Time,
CLKEN
to CLK
Hold Time,
CKLEN
after CLK
LEAB or LEBA Pulse Width
HIGH
(4)
t
W
CLKAB or CLKBA Pulse Width
HIGH or LOW
(4)
t
SK
(o) Output Skew
(3)
P
R
—
—
—
—
E
V
1.0
2.0
1.5
2.5
0
2.5
3.0
—
E
I
—
—
W
—
—
—
—
—
—
—
0.5
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
P
O
R
D
U
T
C
3.0
—
0.5
5.9
5
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