CLKx can accept the following input levels: LVCMOS and
LVTTL
Maximum output frequency: 250MHz
Propagation delay: 1.0ns (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS859S1061I is an16:1 LVCMOS/LVTTL-to-
LVPECL/ LVDS Clock Multiplexer which can operate
HiPerClockS™
up to 250MHz and is a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. Differential output levels can either be selected
to LVDS or LVPECL. The ICS859S1061I has 16 selectable
single-ended clock inputs. The fully differential architecture and
low propagation delay make it ideal for use in clock distribution
circuits. The select pins have internal pulldown resistors. The
CLK_SEL3 pin is the most significant bit and the binary number
applied to the select pins will select the same numbered data input
(i.e., 0000 selects CLK0).
ICS
Table 1A. V
CC_TAP
Function Table
Outputs
Q/nQ
LVPECL
LVPECL
LVDS
LVDS
Output Level Supply
2.5V
3.3V
2.5V
3.3V
V
CC_TAP
V
CC
V
CC
V
CC
Float
Table 1B. SEL_OUT Function Table
Input
SEL_OUT
1
0
Outputs
Q/nQ
LVPECL
LVDS
Block Diagram
CLK_SEL0
Pulldown
CLK_SEL1
Pulldown
CLK_SEL2
Pulldown
CLK_SEL3
Pulldown
CLK0
Pulldown
CLK1
Pulldown
Pin Assignment
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
V
CC_TAP
V
CC
CLK_SEL0
CLK_SEL1
CLK_SEL2
CLK_SEL3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
CLK0
SEL_OUT
V
EE
Q
nQ
OE
nc
Q
nQ
CLK14
Pulldown
CLK15
Pulldown
ICS859S1061I
28-Lead TSSOP, 173MIL
4.4mm x 9.7mm x 0.925
mm
package body
G Package
Top View
OE
Pullup
SEL_OUT
Pullup
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice
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