• Available in 44-pin TSOP II and 400-mil SOJ Pb-Free
Packages
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021D is available in standard 44-pin TSOP Type
II and 400-mil-wide SOJ Pb-Free packages.
Functional Description
[1]
The CY7C1021D is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
SOJ / TSOP II
Top View
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
64K x 16
RAM Array
512 X 2048
I/O
1
–I/O
8
I/O
9
–I/O
16
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
ROW DECODER
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05462 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 11, 2005
PRELIMINARY
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Com’l / Ind’l
Com’l / Ind’l
Com’l / Ind’l
L-Version Only
CY7C1021D-10
10
60
3
1.2
CY7C1021D
CY7C1021D-12
12
50
3
1.2
Unit
ns
mA
mA
Document #: 38-05462 Rev. *C
Page 2 of 10
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
CY7C1021D
DC Input Voltage
[2]
.................................. –0.5V to V
CC
+0.5V
Current into Outputs (LOW)......................................... 20 mA
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5V
±
10%
5V
±
10%
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[2]
......................................–0.5V to V
CC
+0.5V
Electrical Characteristics
Over the Operating Range
7C1021D-10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Test Conditions
Min.
2.4
0.4
2.0
−0.5
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
,
CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
,
f = f
MAX
Max. V
CC
, CE >
V
CC
– 0.3V, V
IN
>
V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
L
−1
−1
V
CC
+ 0.3V
0.8
+1
+1
−300
60
2.0
–0.5
–1
–1
Max.
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
Output Short Circuit
Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-down
Current
—TTL Inputs
Automatic CE
Power-down
Current —CMOS
Inputs
7C1021D-12
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+1
+1
–300
50
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB1
10
10
mA
I
SB2
3
1.2
t
3
1.2
mA
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Thermal Resistance
[4]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[4]
Thermal Resistance
(Junction to Case)
[4]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
All-Packages
TBD
TBD
Unit
°C/W
°C/W
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05462 Rev. *C
Page 3 of 10
PRELIMINARY
AC Test Loads and Waveforms
10-ns Device
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R1 480Ω
5V
3.0V
90%
5 pF
INCLUDING
JIG AND
SCOPE
(c)
167
Equivalent to: THÉVENIN
EQUIVALENT
OUTPUT
R2
255Ω
GND
10%
1.5V
Z = 50Ω
12 -ns Device
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(b)
R 480Ω
CY7C1021D
30 pF*
OUTPUT
R2
255Ω
(a)
ALL INPUT PULSES
90%
10%
Rise Time: 1 V/ns
Fall Time:1 V/ns
167Ω
1.73V
Switching Characteristics
Over the Operating Range
[5]
7C1021D-10
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[9]
t
WC
t
SCE
t
AW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
10
8
7
12
9
8
ns
ns
ns
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[7, 8]
CE LOW to Low Z
[7]
CE HIGH to High Z
[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
0
5
0
10
5
0
6
3
5
0
12
6
0
5
3
6
3
10
5
0
6
100
10
10
3
12
6
100
12
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1021D-12
Min.
Max.
Unit
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the write.
Document #: 38-05462 Rev. *C
Page 4 of 10
PRELIMINARY
Switching Characteristics
Over the Operating Range (continued)
[5]
7C1021D-10
Parameter
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Description
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High
Z
[7, 8]
7
Byte Enable to End of Write
Min.
0
0
7
5
0
3
5
8
Max.
CY7C1021D
7C1021D-12
Min.
0
0
8
6
0
3
6
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR [4]
t
R[10]
Description
V
CC
for Data Retention
Data Retention Current
Non-L, Com’l / Ind’l
L-Version Only
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
Conditions
Min.
2.0
3
1.2
0
t
RC
Max.
Unit
V
mA
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
CE
V
DR
>
2V
4.5V
t
R
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
10. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
µs
or stable at V
CC(min.)
> 50
µs.
11. Device is continuously selected. OE, CE, BHE and/or BHE = V
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