GS88037BT-333/300/250/200
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
256K x 36
9Mb Sync Burst SRAM
333 MHz–200 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
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Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
en
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Applications
The GS88037BT is a 9,437,184-bit (8,388,608-bit for x32
version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
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Parameter Synopsis
t
KQ
tCycle
Curr
(x36)
Curr
(x36)
-333
2.0
3.0
435
435
-300
2.2
3.3
395
395
-250
2.3
4.0
330
330
-200
2.7
5.0
270
270
Unit
ns
ns
mA
mA
N
Pipeline
3-1-1-1
3.3 V
2.5 V
Rev: 1.04 2/2005
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1/19
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r
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88037BT operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 3.3 V and 2.5 V compatible.
N
Functional Description
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
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SCD Pipelined Reads
The GS88037BT is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
D
es
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
© 2002, GSI Technology
GS88037BT-333/300/250/200
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
Type
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
I/O
Data Input and Output pins
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
No Connect
Byte Write—Writes all enabled bytes; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
en
de
d
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
V
DDQ
or V
DD
(must be tied high)
or
Do Not Use (must be left floating)
V
DDQ
/DNU
Rev: 1.04 2/2005
N
ot
R
ec
—
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N
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
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Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
D
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
es
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 2002, GSI Technology
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