H
1.5 – 2.5 GHz LNA Switch PA
Technical Data
HPMX-3003
Features
• GaAs MMIC LNA-Switch-
Power Amp for 1.5 – 2.5 GHz
Transceiver Use
• LNA: 2.2 dB NF, 13 dB G
a
@
1.9 GHz
• Switch: 55 dBm OIP @
1.9 GHz
• Power Amp: +4 dBm in,
+27.5 dBm out, 23.5 dB Gain,
35%
η
add
@ 1.9 GHz
• 3 or 5 V Operation
• JEDEC Standard SSOP-28
Surface Mount Package
Plastic SSOP-28
H
30PMX
YY 03
WW
Description
Hewlett-Packard’s HPMX-3003
combines a Low Noise Amplifier,
GaAs MMIC switch, and 27.5 dBm
power amp in a single miniature
28 lead surface mount plastic
package. This RFIC would
typically serve as the “front end”
and power stage of a battery
operated wireless transceiver for
PCS or ISM band use. Each
section of the RFIC can also be
used independently.
The single-supply LNA makes use
of the low noise characteristics of
GaAs to create a matched, broad-
band amplifier with target perfor-
mance of 13 dB gain and 2.2 dB
noise figure. The switch provides
+55 dBm IP3 for linear operation.
The power amplifier produces up
to 820 mW with 35% power added
efficiency.
The HPMX-3003 is fabricated with
Hewlett-Packard’s GaAs MMIC
process, and features a nominal
0.5 micron recessed Schottky-
barrier-gate, gold metallization,
and silicon nitride passivation to
produce MMICs with superior
performance, uniformity and
reliability.
15 Antenna
C1 14
Package Pin
Configuration
25 PA out
24 Gnd
22 PA out
21 PA out
18 SW2
LNA in 11
27 VG2
26 Gnd
23 Gnd
20 Gnd
19 Gnd
Gnd 10
17 Gnd
16 C2
Gnd 12
SW1 13
28 Gn
Applications
• Personal Communications
Systems (PCS)
• Cordless Telephone Systems
• 2400 MHz Wireless LANs
and ISM Band Spread
Spectrum Applications
Gnd 1
Gnd 2
Gnd 3
VD1 7
LNA out 8
PA in 4
Gnd 5
Gnd 6
HPMX
3003
YYWW
Gnd 9
Functional Block Diagram
LNA out
C1
Antenna
C2
PA in
(VG1)
SW2
PA out
VD1
VG2
VD2
LNA in
SW1
2
HPMX-3003 Absolute Maximum Ratings
[1]
Symbol
P
diss
P
in
V
d
V
cont
T
ch
T
STG
Parameter
Power Dissipation
[2,3]
CW RF Input Power
Device Voltage
Control Voltage
Channel Temperature
Storage Temperature
Units
mW
dBm
V
V
°C
°C
Absolute
Maximum
[1]
LNA
250
[2,3]
+20
8
—
175
-65 to 150
Absolute
Maximum
[1]
Switch
+33
—
-6
175
-65 to 150
Absolute
Maximum
[1]
Power Amp
1500
[2,3]
+20
8
—
175
-65 to 150
Notes:
1. Operation of this device above any of these limits may cause permanent
damage.
2. T
case
= 25°C
3. Derate at 18.2 mW/°C for T
C
> 78°C
Thermal Resistance
[2]
:
θ
jc
= 55°C/W
Recommended operating range of V
cc
= 2.7 to 5.5 V, T
a
= -40 to + 85
°C
HPMX-3003 Standard Test Conditions
Unless otherwise stated, all test data was taken on packaged parts
under the following conditions:
T
a
= 25
°C,
Z
o
= 50
Ω
V
cc
= +3.0 V DC, V
control
= -3.0 V DC, V
D1
= +3.6 V DC
LNA P
in
= -20 dBm, PA P
in
= +4 dBm, frequency = 1.9 GHz
Perfomance cited is performance in test circuit shown in Figure 17.
HPMX-3003 Guaranteed Electrical Specifications
Standard test conditions apply unless otherwise noted.
Symbol
G
test
P
out
I
d
LNA
Parameters and Test Conditions
LNA gain through switch
Output power through switch
LNA bias current
Units
dB
dBm
mA
Min.
9.0
24.0
Typ.
11
25.5
6.5
Max.
9.5
3
HPMX-3003 Summary Characterization Information
Standard test conditions apply unless otherwise noted. All information tested in 1900 MHz
Test Circuit, and reflects performance of test circuit at 1900 MHz.
Symbol
LNA
NF
|S
21
|
2
IRL
ORL
IIP
3
Switch
P
1dB
P
1dB
IP
3
S
21
on
S
21
off
IRL
on
IRL
off
Parameters and Test Conditions
Noise Figure
50
Ω
Gain
Input Return Loss
Output Return Loss
Input Third Order Intercept
Output Power
where insertion loss is increased by 1 dB
∆C1
to C2 = 3 V
Units
dB
dB
dB
dBm
dBm
dBm
dBm
dB
dB
dB
dB
V
D1
= 3.6 V, P
in
= +4 dBm
V
D1
= 3.6 V
V
D1
= 3.6 V, P
in
= +4 dBm
V
D1
= 3.6 V, P
in
= +4 dBm
dB
%
dBm
mA
Typ
2.2
13
15
12
-1
+23
+29
+55
0.8
15
26
0.5
23.5
35
+27.5
450
Output Power
∆C1
to C2 = 5 V
[1]
where insertion loss is increased by 1 dB
Third Order Intercept
Insertion Loss, on channel
Isolation, off channel
Return Loss, on channel
Return Loss, off channel
Power amp
(Vg = -.8 V required)
GP
Gain
η
PAadd
P
out
I
d
PA
Power Added Efficiency
Output Power
Transmit Current
Note:
1. The P
1dB
of the switch can be improved by increasing the difference between the values of C1 and
C2 from the normal 3 V (+23 dB P
1dB
) to 5 V (+29 dB P
1dB
).
HPMX-3003 Pin Description
Gnd 1
Gnd 2
Gnd 3
PA in 4
Gnd 5
Gnd 6
VD1 7
LNA out 8
Gnd 9
Gnd 10
LNA in 11
Gnd 12
SW1 13
C1 14
28 Gn
27 VG2
26 Gnd
25 PA out
24 Gnd
23 Gnd
22 PA out
21 PA out
20 Gnd
19 Gnd
18 SW2
17 Gnd
16 C2
15 Antenna
Figure 1. HPMX-3003 Pin Outs and Schematic.
4
HPMX-3003 Pin Description Table
No. Mnemonic Description
1
2
3
4
Gnd
Gnd
Gnd
PA
in
ground
ground
ground
input to Power
Amplifier
ground
ground
Drain bias
of PA stage 1
output of LNA
Typical Signal
0V
0V
0V
DC: -0.75 V
RF: +4 dBm
0V
0V
+3 V, 100 mA
DC: +3 V, 5 mA
RF: -7 dBm
Description
Short path with minimal parasitics. Ground pins are
also the primary thermal path for heatsinking the device.
Bias through 500
Ω
resistor and 100 pF capacitor. 50
Ω
trans-
mission line with DC blocking capacitor (>24 pF) to input.
Shunt 2.7 pF used on test board to match input at 1.9 GHz.
Short path with minimal parasitics. Ground pins are also
the primary thermal path for heatsinking the device.
Set drain bias to 3 V (can be tied to same rail as PA out).
Bypass with 100 pF capacitor at pin.
Bias through 5 nH choke (printed on PC board) and 100 pF
bypass capacitor to 10
Ω
resistor and 1000 pF bypass
capacitor. Can be operated from 3 to 5 V supply line. 50
Ω
transmission line with DC block (>24 pF) to receiver.
Short path with minimal parasitics. Ground pins are also
the primary thermal path for heatsinking the device.
50
Ω
transmission line from switch. Input blocking capacitor
(24 pF) and shunt 5 nH inductor to ground (noise match at
1.9 GHz) required. Typically a filter is employed between the
LNA input and the switch.
Short path with minimal parasitics. Ground pins are also
the primary thermal path for heatsinking the device.
Switch input or output. Symmetrical with SW2. 50
Ω
transmission line to LNA (or PA). Line should not carry
DC voltage.
High impedance line to control switch, used in conjunction
with C2. C2 should be open when C1 is closed.
50
Ω
transmisson line to/from antenna. Line should not
carry DC voltage.
High impedance line to control switch, used in conjunction
with C1. C1 should be open when C2 is closed.
Short path with minimal parasitics. Ground pins are also the
primary thermal path for heatsinking the device.
Switch input or output. Symmetrical with SW1. 50
Ω
transmission line to PA (or LNA). Line should not carry
DC voltage.
Short path with minimal parasitics. Ground pins are also
the primary thermal path for heatsinking the device.
2.7 pF chip capacitor to ground provides 1.9 GHz output
match for PA. 50
Ω
transmission line to switch. LC choke
and blocking C used. Typically a filter is employed between
the PA output and the switch input.
Short path with minimal parasitics. Ground pins are also
the primary thermal path for heatsinking the device.
Leave unconnected; use pins 21 & 22 for PA out.
Short path with minimal parasitics. Ground pins are also
the primary thermal path for heatsinking the device.
Provide bias through 10
Ω
resistor. Bypass to ground at pin
with 10 pF capacitor, and on power supply side of resistor
with 1000 pF capacitor.
Short path with minimal parasitics. Ground pins are also the
primary thermal path for heatsinking the device.
5
6
7
8
Gnd
Gnd
VD1
LNA out
9
10
11
Gnd
Gnd
LNA in
ground
ground
input of LNA
0V
0V
DC: 0 V
RF: -20 dBm
12
13
Gnd
SW1
ground
switch
terminal 1
switch control 1
switch center
pole
switch control 2
ground
switch
terminal 2
ground
ground
output of PA
output of PA
0V
DC: 0 V
RF: -20 dBm
closed: 0 V
open: -3 to -5 V
DC: 0 V
RF: +26 dBm
closed: 0 V
open: -3 to -5 V
0V
DC: 0 V
RF: +4 dBm
0V
0V
DC: 3 V, 350 mA
RF: +27 dBm
14
15
16
17
18
C1
Antenna
C2
Gnd
SW2
19
20
21
22
Gnd
Gnd
PA out
PA out
23
24
25
26
27
Gnd
Gnd
PA out
Gnd
VG2
ground
ground
output of PA
ground
Gate bias on
PA stage 2
ground
0V
0V
DC: 3 V, 350 mA
RF: +27 dBm
0V
-0.75 V
28
Gnd
0V
5
HPMX-3003 Typical Performance
Standard test conditions apply unless otherwise noted. 2.4 GHz performance is performance in test circuit
shown in Figure 18. Some aspects of performance are determined by the test circuit impedances.
10
9
8
CURRENT (mA)
NOISE FIGURE (dB)
20
5
7
6
5
4
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
GAIN (dB)
15
2400 MHz
1900 MHz
4
3
2400 MHz
10
2
1900 MHz
5
1
0
2.5
3
3.5
4
4.5
5
5.5
6
0
2.5
3
3.5
4
4.5
5
5.5
6
VOLTAGE (V)
VOLTAGE (V)
VOLTAGE (V)
Figure 2. LNA Current vs. Device
Voltage at 1900 MHz.
Figure 3. LNA Gain vs. Device Voltage
and Frequency.
Figure 4. LNA Noise Figure vs. Device
Voltage and Frequency.
8
7
20
5
4
NOISE FIGURE (dB)
6
CURRENT (mA)
GAIN (dB)
15
5
4
3
2
1
0
-60 -40 -20
0
20
40
60
80 100
3
10
2
5
1
0
-60 -40 -20
0
20
40
60
80 100
0
-60 -40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. LNA Current vs.
Temperature at 1900 MHz.
Figure 6. LNA Gain vs. Temperature
at 1900 MHz.
Figure 7. LNA Noise Figure vs.
Temperature at 1900 MHz.
12
35
1900 MHz
30
50
10
CURRENT (mA)
Stg 2
Pout (dBm)
40
25
20
15
10
2400 MHz
PAE (%)
1900 MHz
30
8
6
20
2400 MHz
10
4
Stg 1
2
2.5
5
0
2.5
3
3.5
4
4.5
5
5.5
6
3
3.5
4
4.5
5
5.5
6
0
2.5
3
3.5
4
4.5
5
5.5
6
VOLTAGE (V)
VOLTAGE (V)
VOLTAGE (V)
Figure 8. PA Current vs. Device
Voltage at 1900 MHz.
Figure 9. PA Output Power vs. Supply
Voltage and Frequency.
Figure 10. PA Power Added Efficiency
vs. Supply Voltage and Frequency.
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