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STK15C88-N45

产品描述Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOIC-28
产品类别存储    存储   
文件大小32KB,共4页
制造商Simtek
官网地址http://www.simtek.com
下载文档 详细参数 全文预览

STK15C88-N45概述

Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOIC-28

STK15C88-N45规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Simtek
包装说明SOP, SOP28,.4
Reach Compliance Codeunknown
ECCN代码EAR99
最长访问时间45 ns
其他特性EEPROM SOFTWARE STORE; SOFTWARE RECALL; STORE CYCLE = 100000
JESD-30 代码R-PDSO-G28
JESD-609代码e0
长度17.935 mm
内存密度262144 bit
内存集成电路类型NON-VOLATILE SRAM
内存宽度8
湿度敏感等级3
功能数量1
端口数量1
端子数量28
字数32768 words
字数代码32000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织32KX8
输出特性3-STATE
可输出YES
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP28,.4
封装形状RECTANGULAR
封装形式SMALL OUTLINE
并行/串行PARALLEL
峰值回流温度(摄氏度)240
电源5 V
认证状态Not Qualified
座面最大高度2.64 mm
最大待机电流0.003 A
最大压摆率0.065 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
宽度7.505 mm
Base Number Matches1

文档预览

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Applying the STK11C88, STK15C88
and STK16C88 32K x 8 nvSRAM
Abstract
Simtek Corporation’s family of high speed 256 kilobit
nonvolatile Static Random Access Memories
includes the STK15C88
AutoStore™
and
STK11C88 Software Store and STK16C88
AutoStorePlus™
devices. All three memories have
industry-standard 32K x 8 architectures and pin-outs
(Figure 1), and are drop-in replacements for many
standard SRAM and BatRAM products. As with all
Simtek nvSRAM products, the STK11C88,
STK15C88 and STK16C88 do not require batteries
or other power sources to maintain nonvolatility for a
guaranteed minimum of 100 years, even at high
temperatures.
The STK15C88
AutoStore™
and STK16C88
AutoStorePlus™
memories both automatically
STORE
the SRAM data into EEPROM upon power
loss, and require no external power storage compo-
nents such as batteries or capacitors. They are
available in speeds of 20, 25, 35, and 45 nanosec-
onds.
The STK11C88 Software Store memory is designed
for safe storage of data under processor control.
The STK11C88 virtually eliminates the danger of
inadvertent data loss due to human error or elec-
tronics failure. It is ideally suited for applications that
would normally require the combination of high
speed SRAM and EEPROM, and performs both
functions in one package. The resultant savings in
board space, glue logic (parts count), and power
consumption helps to reduce costs and increase
packaging density. The STK11C88 is available in
20, 25, 35, and 45 nanosecond versions, and can
be interfaced to most standard microprocessors
without interface logic or memory wait states.
Both memories automatically
RECALL
nonvolatile
data into the SRAM portion of the chip at power-up
without processor intervention or external control.
Simtek's family of nonvolatile memories give the
product development engineer the ability to design
modern embedded and state machines without the
worry of data loss or corruption due to power failure.
SRAM Operations
The STK11C88, STK15C88 and STK16C88 nvS-
RAM memories are identical in the operation of their
RAM front ends, and look to the design engineer like
industry standard 32K x 8 fast SRAMs.
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
Figure 1
STK11C88/STK15C88/STK16C88 Pin-Out
The three control lines, Write Enable (W), Chip
Enable (E), and Output Enable (G) are utilized in the
same manner as a standard SRAM. This front end
functional equivalency allows improvements to be
made to old designs without PWB (Printed Wiring
Board) or control logic changes. The ability of
Simtek's nvSRAM devices to run at processor bus
speeds eliminates the need for wait states, bus con-
trol logic, or specialized decoder circuitry. This com-
bination of speed and versatility in one package
serves to simplify board layout and reduce device
count.
SRAM Reads are performed whenever E and G are
low and W is high. The output data on lines DQ
0
-
DQ
7
corresponds to the address specified on pins
A
0
- A
14
.
SRAM Writes are performed whenever E and W are
low. The data on pins DQ
0
- DQ
7
will be written into
memory at the location specified by the address
present on lines A
0
- A
14
. The G (Output Enable)
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