512K x 32 SRAM MODULE
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
PUMA 68S16000/A-020/025/35/45
Issue 4.3 : November 1998
Features
•
Very Fast Access Times of 20,25,35,45 ns.
• JEDEC 68 'J' leaded plastic Surface Mount
Substrate.
• Commercial, Industrial, or Military Grade.
• User Configurable as 8 / 16 / 32 bit wide
output.
• Operating Power :
• Standby Power : -L Part
• Fully Static operation.
• Single 5V±10% Power supply.
2.86 W (max)
44 mW (max)
Description
The PUMA 68S16000 is a 16Mbit CMOS High
Speed Static RAM in a JEDEC 68 pin surface
mount PLCC, available with access times of 20, 25,
35, and 45ns. The output width is user configurable
as 8 , 16 or 32 bits using four Chip Selects (CS1~4).
The device is available with the option of
independant or single WE control. The plastic de-
vice is screened to ensure high reliability.
The device features low power standby, multiple
ground pins for maximum noise immunity and TTL
compatible inputs and outputs. The PUMA
68S16000 offers a dramatic space saving advan-
tage over four standard 512Kx8 devices.
Block Diagram (see sheet 7 for 'A' version)
Pin Definition (see sheet 7 for 'A' version)
GND
CS3
CS4
NC
WE
VCC
A10
A9
A0
A1
A2
A3
A4
A5
A6
A0~A18
OE
WE
D0
D1
D2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
D3
D4
D5
D6
PUMA 68S16000
VIEW
FROM
ABOVE
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
VCC
A8
NC
A7
GND
A17
CS1
A11
CS2
A13
A14
A18
OE
NC
NC
A12
A15
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A18
D0 - D31
CS1~4
WE
OE
NC
V
CC
GND
Package Details
Plastic 68 J-Leaded JEDEC PLCC
A16
NC
ISSUE 4.3 : November 1998
PUMA 68S16000/A-020/025/35/45
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T(2)
P
T
T
STG
Min
-0.5
-
-65
Typ
-
-
-
Max
7.0
5.0
150
Unit
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) V
T
can be -3.0V pulse of less than 10ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
Min
4.5
2.2
-0.3
0
-40
-55
Typ
5.0
-
-
-
-
-
Max
5.5
V
CC
+0.5
0.8
70
85
125
Unit
V
V
V
o
C
o
C (Suffix I)
o
C (Suffix M)
(Commercial)
(Industrial)
(Military)
DC Electrical Characteristics
(V
CC
=5V±10%, T
A
= -55
o
C to +125
o
C)
Parameter
I/P Leakage Current
Symbol Test Condition
Address,OE,WE
Min Typ
-20
-20
-
-
-
-
-
-
-
2.4
-
-
-
-
-
-
-
-
-
-
max Unit
20
20
720
480
360
240
40
4
0.4
-
µA
µA
mA
mA
mA
mA
mA
mA
V
V
I
LI
I
LO
I
CC32
I
CC16
I
CC8
I
SB1
I
SB2
I
SB3
V
OL
V
OH
0V < V
IN
< V
CC
CS = V
IH,
V
I/O
= GND to V
CC
Min. Cycle, CS = V
IL
, f=f
MAX
, I
OUT
= 0mA
As Above.
As Above.
CS = V
IH
, f=f
MAX
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V, f=0
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V, f=0
I
OL
= 8.0mA
I
OH
= -4.0mA
Output Leakage Current
Operating Supply Current
32-bit mode
16-bit mode
8-bit mode
Standby Supply Current
TTL levels
CMOS levels
-L Version (CMOS)
Output Voltage
Notes :
1/ Typical values are at V
CC
=5.0V,T
A
=25
o
C and specified loading.
2/ CS above refers to CS1~4.
3/ At f=f
MAX
address and data inputs are cycling at maximum frequency.
2
PUMA 68S16000/A-020/025/35/45
ISSUE 4.3 : November 1998
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Note: Capacitance calculated, not measured.
Parameter
Input Capacitance
(Address,OE,WE)
I/P Capacitance
(other)
I/O Capacitance
Symbol Test Condition
C
IN1
C
IN2
C
I/O
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
max
30
7
38
Unit
pF
pF
pF
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
Operation Truth Table
I/O Pin
645
Ω
1.76V
100pF
CS
H
L
L
L
L
OE
X
L
H
L
H
WE
X
H
L
L
H
DATA PINS
High Impedance
Data Out
Data In
Data In
High-Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
, I
SB3
I
CC32
, I
CC16
, I
CC8
I
CC32
, I
CC16
, I
CC8
I
CC32
, I
CC16
, I
CC8
I
SB1
, I
SB2
, I
SB3
CS above refers to CS1~4.
MODE
Standby
Read
Write
Write
High-Z
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
Low V
cc
Data Retention Characteristics - L Version Only
Parameter
V
CC
for Data Retention
Data Retention Current
Symbol
V
DR
Test Condition
CS > V
CC
-0.2V
V
CC
=3.0V, CS>V
CC
-0.2
See Retention Waveform
See Retention Waveform
min
2.0
-
0
t
RC
typ
(1)
-
-
-
max
-
2
-
-
Unit
V
mA
ns
ms
I
CCDR1 (1,2)
Chip Deselect to Data Retention Time
t
CDR
Operation Recovery Time
t
R
Notes
(1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
3
ISSUE 4.3 : November 1998
PUMA 68S16000/A-020/025/35/45
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
-020
min max
20
-
-
-
4
3
0
0
0
-
20
20
10
-
-
-
8
8
-025
min max
25
-
-
-
5
3
0
0
0
-
25
25
12
-
-
-
10
10
-35
min max
35
-
-
-
6
3
0
0
0
-
35
35
14
-
-
-
12
12
-45
min max
45
-
-
-
7
3
0
0
0
-
45
45
16
-
-
-
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
-020
min max
20
15
15
0
15
0
0
9
0
4
-
-
-
-
-
-
8
-
-
-
-025
min max
25
20
20
0
20
0
0
10
0
5
-
-
-
-
-
-
10
-
-
-
-35
min max
35
25
25
0
25
0
0
12
0
7
-
-
-
-
-
-
12
-
-
-
min
45
35
35
0
35
0
0
14
0
9
-45
max Unit
-
-
-
-
-
-
14
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
PUMA 68S16000/A-020/025/35/45
ISSUE 4.3 : November 1998
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS1~4
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS1~4
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
DH
t
OW
(8)
Dout
High-Z
Din
Data Valid
5
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