Using the SIMTEK STK12C68
and STK14C88
AutoStore
TM
High
Performance Nonvolatile Static RAM
Introduction
Simtek Corporation’s STK12C68 and STK14C88
are both fast static RAMs backed by their own non-
volatile EEPROM shadow memory. The 8K x 8
STK12C68 is available in an industry standard 28
pin package; the 32K x 8 STK14C88 comes in 32
pin packages. In both cases, the SRAM portion of
memory operates similarly to other byte-wide fast
SRAM products and is easily interfaced to embed-
ded processors and logic elements. The uniqueness
of Simtek’s nvSRAMs is their ability to
STORE
data
indefinitely without the need of batteries or other
power sources. SRAM data can be
Stored
into non-
volatile memory under hardware or software control
and is autonomously saved upon power-down. The
entire memory array is automatically
Recalled
upon
power-up without the need for processor interven-
tion or the generation of external control signals.
Data is
Stored
and
Recalled
in parallel, resulting in
very fast nonvolatile operations (high bandwidth)
that are ideally suited to a broad range of embedded
processor and state machine applications.
This feature is locked out by internal logic if SRAM
data hasn’t changed since the last nonvolatile
STORE
or
RECALL.
HSB also serves as a “Store
Operation Busy” monitor line that is internally driven
low during all nonvolatile
STORE
operations. If HSB
is loaded by the system, it should be pulled to Sys-
tem V
CC
through a 10kΩ resistor to help eliminate
noise-induced
STORE
operations and to assure a
true logic high when not in an active condition (See
Figure1 for example). If the system does not moni-
tory HSB, then the pin should NOT be connected to
anything: the chip’s internal circuitry can easily drive
the package capacitance.
10kΩ
1
28
27
26
68µF
6v, ±20%
+
Design, Packaging and Board Layout
Considerations
The STK12C68 comes in four industry standard 28
pin package styles: 300-mil DIP, 600-mil DIP, 300
mil SOIC and 350-mil SOIC (Gull Wing). The
STK14C88 comes in two 32 pin package styles:
300-mil DIP, and 300-mil SOIC (Gull Wing). Both are
available in commercial and industrial temperature
ranges in plastic packages, and in the military tem-
perature range in ceramic. While the 12C68 pin-out
for address, data, and control conforms to industry
standard packaging for fast SRAM, it must be noted
that the 12C68 has only one chip select rather than
the normal two. This was done to accommodate a
control line to initiate and monitor hardware
STORE
operations. The STK14C88 comes in a 32 pin pack-
age also to make room for the hardware
STORE
monitoring pin. The Hardware-Store-Busy pin (HSB)
is a bi-directional control line that starts nonvolatile
STORE
operations if taken low by external circuitry.
0.1µF
Bypass
14
Figure 1A
Typical STK12C68 Configuration
10kΩ
1
32
31
30
F
68µF
6v, ±20%
+
0.1µF
Bypass
16
17
Figure 1B
Typical STK14C88 Configuration
8-13
10kΩ
10kΩ
Using the STK12C68 and STK14C88
The resistor suggested on W in Figure 1 is to pre-
vent accidental SRAM writes over the
Recalled
data
in systems that are still unstable above V
SWITCH
on
power-up.
If the STK12C68 is being used to replace single
Chip Select slow SRAM (batRAM, etc.), PCB, cir-
cuitry, and logic changes are minimal. The addition
of a 68µF capacitor from V
CAP
(pin 1) to ground, and
appropriate logic changes to handle Hardware Store
Operations (pin 26), if desired, are all that are nec-
essary to implement the full capabilities of the
12C68. The STK14C88 requires analogous
changes, in addition to adjustments for the higher
pin count.
As with any high speed SRAM, a good quality (low
inductance) decoupling capacitor is required from
chip power to ground. Since the internal circuitry of
both the STK12C68 and STK14C88 is powered
from V
CAP
, the decoupling capacitor must be con-
nected from pin 1 to ground. Lead lengths should be
kept short to minimize stray inductance and to pro-
vide a low impedance path to ground for high fre-
quency noise.
The STK12C68 and STK14C88 ease manufacturing
and package layout problems associated with other
manufacturers’ NVRAMs. Simtek’s standard pack-
age dimensions (including height) allow the usage
of automated pick and place machines and standard
PCB layouts. The STK12C68 and STK14C88 do not
contain batteries so they can be flow soldered which
eliminates the need for costly manual operations.
case, a 68µF capacitor is not needed because the
STK12C68/STK14C88 simply uses the system
power to execute the
STORE
cycle. (Note that this
configuration is functionally equivalent to the
STK15Cxx family which is available in 28 pin pack-
ages. The
AutoStorePlus™
family adds system
power slew rate independence.)
10kΩ
1
28
27
26
0.1µF
Bypass
14
Figure 2A
STK12C68 connected to rely on system power
for
AutoStore™
10kΩ
1
32
31
30
V
CC
Connection Options
The STK12C68 and STK14C88 can be connected
to V
CC
in one of three ways, depending on system
characteristics and requirements. The most com-
mon connection, illustrated in Figure 1, involves the
use of a 68µµF capacitor on the V
CAP
pin (pin 1).
This connection scheme guarantees that an
AutoStore™
will occur on power-down (if the SRAM
has been written), using the charge stored in the
68µF capacitor to complete the
STORE
cycle. When
V
CC
drops below V
SWITCH
, the STK12C68/
STK14C88 disconnects itself from the system power
bus and executes a
STORE
cycle, saving the SRAM
data to the EEPROM array in less than 10ms.
Figure 2 shows a V
CC
connection that still enables
an
AutoStore™
when V
CC
collapses, but requires
that the system V
CC
remain between V
SWITCH
(min-
imum) and 3.5V for at least 10 milliseconds. In this
0.1µF
Bypass
16
17
Figure 2B
STK14C88 connected to rely on system power
for
AutoStore™
Figure 3 illustrates a connection that will prevent
AutoStores™
from ever occurring. By permanently
grounding V
CCX
(pin 28/32) and connecting system
V
CC
directly to V
CAP
(pin 1), the internal power FET
between pins 1 and 28/32 is held off and
AutoStores™
are disabled. In this configuration, the
user can still initiate
Stores
through either address
sequences or by pulling the HSB pin low.
Note that it is not permissible to change between
these three options “on the fly”. Specifically, con-
necting up VCC as shown in Figure 1 or 2 and then
changing to the connection in Figure 3 is forbidden.
If this is attempted, it is very likely that the device will
8-14
10kΩ
10kΩ
Using the STK12C68 and STK14C88
be destroyed due to high current flow through the
internal power FET which, under certain conditions,
can effectively remain on for several seconds after
power is removed from the part.
10kΩ
10kΩ
1
28
27
26
A write to SRAM is performed whenever E and W
are low, and HSB is high. The data on pins DQ
0
-
DQ
7
will be written into the memory cells corre-
sponding to the address present on pins A
0
-A
1X
. It is
suggested that the control line G (output enable) be
held high during the entire write cycle to avoid a
possible data bus contention on the common I/O
lines.
If the STK12C68 is being used as an SRAM
replacement in an existing design, a PWB or control
logic modification may be required to accommodate
the single Chip Enable (E), and the Hardware-Store-
Busy (HSB) pins.
0.1µF
Bypass
14
Nonvolatile Recall Operations
Nonvolatile
RECALL
operations can be initiated in
two different ways: (1) Software, and (2) Automatic
power-up
RECALL.
Figure 3A
STK12C68 in
AutoStore™
Inhibit Mode
0.1µF
Bypass
10kΩ
1
32
31
30
10kΩ
1. Software Initiated
RECALL
A
RECALL
of data from nonvolatile memory to
SRAM is accomplished in a manner similar to the
software
STORE
operation. A series of six
addresses are read in an uninterrupted fashion to
begin the
RECALL.
The addresses must be read in
the following order:
Read
12C68
0000H
1555H
0AAAH
1FFFH
10F0H
0F0EH
14C88
0E38H
31C7H
03E0H
3C1FH
303FH
0C63H
RECALL
Start
16
1
17
2
Figure 3B
STK14C88 in
AutoStore™
Inhibit Mode
The pull-up on HSB is only required if the pin is
loaded by the system itself, in order to assist the
internal chip pull-up against the system load. If the
system does not monitor or drive HSB, the pin
should be left unconnected. The resistor on W is
necessary in systems that are still unstable on
power-up above V
SWITCH
: if W is still floating at that
time, the resistor will prevent accidental SRAM
writes over the freshly
Recalled
data.
3
4
5
6
2. Power-Up Initiated Recall
The STK12C68/STK14C88 automatically
Recalls
the data
Stored
in nonvolatile memory upon power-
up. Internal control logic initiates the
RECALL
when
system V
CC
rises above V
SWITCH
.
SRAM Operations
The high speed of the SRAM section of the
STK12C68/STK14C88 operates similarly to other
fast SRAMs on the market today. SRAM reads are
performed whenever E and G are low, and HSB and
W are high. The output data corresponds to the
address specified on pins A
0
-A
1X
.
Nonvolatile Store Operations
Nonvolatile Store operations can be initiated in three
different ways on the STK12C68/STK14C88: (1)
Hardware, (2) Software, and (3) Automatically on
power-loss
STORE
(AutoStore™).
8-15
Using the STK12C68 and STK14C88
1. Hardware Store
Hardware
Stores
can be initiated externally by pull-
ing the HSB pin low for a minimum of 15ns. Internal
circuitry will then keep the pin low for the duration of
the
STORE
operation. Care should be exercised to
assure that HSB is not externally pulled high until
after the
STORE
has completed and the internal
logic has released the pin. During Stores pins DQ
0
-
DQ
7
assume a high impedance output condition and
remain tri-stated until the operation completes
(10ms maximum). Internal control logic prevents the
12C68/14C88 from performing additional Hardware
STORE
operations if no SRAM write has taken
place since the last
STORE
or
RECALL
cycle. This
helps eliminate the chance of multiple
STORE
oper-
ations during power-up or because of noise on the
HSB pin.
Hardware-Store-Busy (HSB) is a high speed, low
drive capability bi-directional control pin. If it is
loaded by the system, it is important that HSB be
pulled to V
CAP
through a suitable pull-up resistor
(10kΩ typical) to assure that
STORE
operations are
not initiated by noise, or during bus direction transi-
tions. The HSB pull-up resistor serves to lower the
line impedance and helps to control induced noise
that could initiate undesired
STORE
operations.
Due to the weak output drive capability of the HSB
pin, it is important that the pull-up resistor value be
selected carefully so as not to swamp the output
driver. While this will not cause damage to the chip,
it could inhibit the STK12C68/STK14C88’s auto-
matic power loss
STORE
capability (AutoStore™)
and could result in inadvertent data loss. If HSB is
not required by the system, the pin should be left
unconnected.
Read
3
4
5
6
12C68
0AAAH
1FFFH
10F0H
0F0EH
14C88
03E0H
3C1FH
303FH
0FC0H
STORE
Start
Note that the HSB pin stays low during the duration
of the Software
STORE.
3. Automatic Power-Loss
STORE
(AutoStore™)
If a 68µF capacitor is connected between V
CAP
and
ground, and power is applied to V
CCX
(see Figure
1), the STK12C68/STK14C88 will automatically
STORE
the SRAM data to nonvolatile memory upon
power loss. V
CAP
is automatically disconnected
from system V
CCX
by an internal power FET when
system power drops below V
SWITCH
. Current is then
drawn from the storage capacitor during the
STORE
operation. This function is completely automatic and
requires no external commands.
If the system power supply has sufficient output
capacitance to assure that V
CC
will not decay from
V
SWITCH
(minimum) to 3.5 volts in less than 10ms,
the energy storage capacitor can be eliminated.
With system V
CC
tied to both V
CAP
and V
CCX
(Fig-
ure 2) the STK12C68/STK14C88 will perform an
AutoStore™
every time V
CC
drops below V
SWITCH
,
assuming an SRAM Write has taken place since the
last nonvolatile cycle.
If automatic power down
Stores
are not required,
the 68µF energy storage capacitor can be elimi-
nated (Figure 3). System V
CC
is then tied directly to
V
CAP
and V
CCX
is grounded. This will disable the
AutoStore™
function but will still allow nonvolatile
Stores
to be initiated via the HSB pin or under soft-
ware control.
2. Software Store
Data can be
Stored
into the nonvolatile memory on
the STK12C68/STK14C88 under software control.
This process involves the reading of six addresses
in sequence to begin the
STORE.
It is important to
assure that Read operations are performed instead
of Writes or the store will not occur. Software
STORE
takes place regardless of whether an SRAM
Write took place since the last nonvolatile cycle. The
address locations to be read are:
Read
1
2
12C68
0000H
1555H
14C88
0E38H
31C7H
Low Power Operation
The STK12C68/STK14C88 is designed to use mini-
mum power when the Chip Enable pin, E, is not
asserted. During this time the chip consumes only
standby current. Total chip power dissipation during
operation is determined by several factors, the most
important of which is system access cycle time. The
faster the memory is accessed, the higher the cur-
rent requirements of the chip. Secondly, use of TTL
or CMOS input levels has an effect on total power
requirements. At CMOS input signal levels the
8-16
Using the STK12C68 and STK14C88
STK12C68 consumes less power than it does when
driven with TTL levels. Other factors affecting power
dissipation include V
cc
voltage level and operating
temperature.
The STK12C68/STK14C88 is designed to minimize
power automatically by internally shutting down
unnecessary circuitry during read operations.
Approximately 45ns after E goes low, current will
drop to standby level.
It can be seen from Figure 4 that the changes
required to switch from the Dallas Semiconductor
DS1225Y to the SIMTEK STK12C68
AutoStore™
are minimal. The 68µF
AutoStore™
capacitor may
be eliminated if the system power decay time is
greater than 10ms between V
SWITCH
(minimum)
and 3.5 volts. (The above Figure 2 configuration is
functionally equivalent to the STK15Cxx family. The
new
AutoStorePlus™
family adds power supply
skew immunity, just like the Figure 1 configuration.)
Conclusion
The Simtek STK12C68/STK14C88 is a high perfor-
mance nonvolatile SRAM that is a perfect fit for
applications requiring high speed, nonvolatile mem-
ory. Its ease of insertion makes it a natural choice
where batteries and other nonstandard packaging
concerns rule out other technologies. Its high speed
allows it to operate where other technologies
(batRAM, Flash, EEPROM) can’t, such as embed-
ded DSP and other fast processor applications. Its
exceptionally long data retention times even at high
temperatures and high reliability make it a natural
choice for users that require secure data retention,
such as is found in the military, financial, and gam-
ing industries.
10kΩ
10kΩ
28
27
1
28
27
26
10kΩ
28
27
0.1µF
Bypass
68µF
6v, ±20%
+
14
0.1µF
Bypass
Dallas
DS1225Y
Simtek
STK12C68
Simtek
STK16C68
14
14
Figure 4
Comparison between Dallas DS1225Y, Simtek STK12C68 and Simtek STK16C68
8-17
0.1µF
Bypass
10kΩ
微控制器 MCU
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