STK12C68
8K x 8
AutoStore™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
• “Hands-off” Automatic
STORE
with External
68µF Capacitor on Power Down
•
STORE
to EEPROM Initiated by Hardware,
Software or
AutoStore™
on Power Down
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Single 5V + 10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 28-Pin SOIC and DIP Packages
DESCRIPTION
The Simtek STK12C68 is a fast static
RAM
with a
nonvolatile, electrically erasable
PROM
element
incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM
. Data transfers from the
SRAM
to the
EEPROM
(the
STORE
operation) can take place
automatically on power down. A 68µF or larger
capacitor tied from V
CAP
to ground guarantees the
STORE
operation, regardless of power-down slew
rate or loss of power from “hot swapping”. Transfers
from the
EEPROM
to the
SRAM
(the
RECALL
opera-
tion) take place automatically on restoration of
power. Initiation of
STORE
and
RECALL
cycles can
also be software controlled by entering specific read
sequences. A hardware
STORE
may be initiated with
the HSB pin.
BLOCK DIAGRAM
V
CCX
V
CAP
POWER
CONTROL
PIN CONFIGURATIONS
V
CAP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
EEPROM ARRAY
128 x 512
A
5
ROW DECODER
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
128 x 512
RECALL
STORE/
RECALL
CONTROL
HSB
V
CCX
W
HSB
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 600 PDIP
28 - 350 SOIC
28 - 300 CDIP
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
- A
12
PIN NAMES
A
0
- A
12
DQ
0
-DQ
7
E
W
Address Inputs
Data In/Out
Chip Enable
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
Ground
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
G
HSB
V
CCX
V
CAP
V
SS
July 1999
4-41
STK12C68
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to V
SS
. . . . . . . . . .–0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB . . . . . . . . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC
c
1
(V
CC
= 5.0V
±
10%)
b, f
INDUSTRIAL
UNITS
MIN
MAX
100
90
75
65
3
10
2
32
27
23
20
1.5
±1
±5
2.2
V
SS
– .5
2.4
0.4
0.4
0
70
– 40
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
0.4
85
MIN
MAX
N/A
90
75
65
3
10
2
N/A
28
24
21
1.5
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
V
°C
t
AVAV
= 20ns
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
AVAV
= 20ns, E
≥
V
IH
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA except HSB
I
OUT
= 8mA except HSB
I
OUT
= 3mA
NOTES
PARAMETER
Average V
CC
Current
I
CC
I
CC
I
CC
I
SB
d
2
c
3
d
4
e
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CAP
Current during
AutoStore™
Cycle
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
1
I
SB
e
2
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
V
BL
T
A
Note b:
Note c:
Note d:
Note e:
Note f:
The STK12C68-20 requires V
CC
= 5.0V
±
5% supply to operate at specified speed.
I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
I
CC
and I
CC
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
4
E
≥
2
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
V
CC
reference levels throughout this datasheet refer to V
CCX
if that is where the power supply connection is made, or V
CAP
if V
CCX
is con-
nected to ground.
5.0V
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
480 Ohms
OUTPUT
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
CAPACITANCE
g
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
8
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
Note g: These parameters are guaranteed but not tested.
Figure 1
:
AC Output Loading
July 1999
4-42
STK12C68
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
1
2
3
4
5
6
7
8
9
10
11
t
ELQV
t
AVAVh
t
AVQVi
t
GLQV
t
AXQXi
t
ELQX
t
EHQZj
t
GLQX
t
GHQZj
t
ELICCHg
t
EHICCLg
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
7
0
25
5
5
7
0
10
0
35
20
22
8
5
5
10
0
13
0
45
PARAMETER
MIN
MAX
20
25
25
10
5
5
13
0
15
MIN
MAX
25
35
35
15
5
5
15
MIN
MAX
35
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK12C68-20
STK12C68-25
(V
CC
= 5.0V
±
10%)
b, f
STK12C68-35
STK12C68-45
UNITS
Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with E and G both low.
Note j: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
h, i
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
3
t
AVQV
DATA VALID
SRAM READ CYCLE #2:
E Controlled
h
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
7
6
1
2
t
EHICCL
1
1
G
4
t
GLQV
t
GHQZ
9
t
GLQX
DQ (DATA OUT)
t
ELICCH
I
CC
STANDBY
10
DATA VALID
8
ACTIVE
July 1999
4-43
STK12C68
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ j, k
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
MIN
20
15
15
8
0
15
0
0
7
5
MAX
MIN
25
20
20
10
0
20
0
0
10
5
MAX
MIN
35
25
25
12
0
25
0
0
13
5
MAX
MIN
45
30
30
15
0
30
0
0
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK12C68-20
STK12C68-25
(V
CC
= 5.0V
±
10%)
b, f
STK12C68-35
STK12C68-45
UNITS
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E or W must be
≥
V
IH
during address transitions.
Note m: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1:
W Controlled
l, m
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
l, m
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
July 1999
4-44
STK12C68
HARDWARE MODE SELECTION
E
H
L
L
X
W
X
H
L
X
HSB
H
H
H
L
A
12
- A
0
(hex)
X
X
X
X
0000
1555
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
MODE
Not Selected
Read SRAM
Write SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
I/O
Output High Z
Output Data
Input Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
POWER
Standby
Active
Active
l
CC
2
NOTES
p
n
L
H
H
Active
o, p
l
CC
2
L
H
H
Active
o, p
Note n: HSB
STORE
operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the
STORE
(if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
Note o: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note p: I/O state assumes G < V
IL
. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE
STORE
CYCLE
SYMBOLS
NO.
Standard
22
23
24
25
26
t
STORE
t
DELAY
t
RECOVER
t
HLHX
t
HLBL
Alternate
t
HLHZ
t
HLQZ
t
HHQX
STORE
Cycle Duration
Time Allowed to Complete SRAM Cycle
Hardware
STORE
High to Inhibit Off
Hardware
STORE
Pulse Width
Hardware
STORE
Low to Store Busy
PARAMETER
(V
CC
= 5.0V
±
10%)
b, f
STK12C68
UNITS NOTES
MIN
MAX
10
1
700
15
300
ms
µs
ns
ns
ns
j, q
j, r
q, s
Note q: E and G low for output behavior.
Note r: E and G low and W high for output behavior.
Note s: t
RECOVER
is only applicable after t
STORE
is complete.
HARDWARE
STORE
CYCLE
25
t
HLHX
HSB (IN)
24
t
RECOVER
22
t
STORE
HSB (OUT)
HIGH IMPEDANCE
26
t
HLBL
HIGH IMPEDANCE
23
t
DELAY
DQ (DATA OUT)
DATA VALID
DATA VALID
July 1999
4-45
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