STK25CA8
128K x 8
AutoStore™
nvSRAM
High Performance CMOS
Nonvolatile Static RAM Module
ADVANCE
FEATURES
• Nonvolatile Storage Without Battery Problems
• Directly Replaces 128K x 8 static RAM, Battery
Backed RAM or EEPROM
• 45ns and 55ns Access Times
• Store to EEPROM Initiated by
AutoStore™
on
Power Down
• Recall to SRAM by Power Restore
• 22mA I
CC
at 200ns Cycle Time
• Unlimited Read, Write and Recall Cycles
• 100,000 Store Cycles to EEPROM
• 10 Year Data Retention Over Full Industrial
Temperature Range
• Commercial and Industrial Temp. Ranges
• 32 Pin 600 Dual In-Line Module
DESCRIPTION
The Simtek STK25CA8 is a fast static RAM with a
nonvolatile, electrically-erasable PROM element
incorporated in each static memory cell. The SRAM
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the
STORE
operation) can take place
automatically on power down using charge stored in
system capacitance. Transfers from the EEPROM to
the SRAM (the
RECALL
operation) take place auto-
matically on restoration of power.
BLOCK DIAGRAM
A
15
A
16
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
MODULE
DECODER
VCC
PIN CONFIGURATION
NC
A
16
A
14
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
NC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
EEPROM ARRAY
512 x 512 x 4
STORE
ROW DECODER
POWER
CONTROL
STORE/
RECALL
CONTROL
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
STATIC RAM
ARRAY
512 x 512 x 4
RECALL
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
V
SS
32 - 600 mil Dual In-Line Module
PIN NAMES
A
0
- A
16
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+5V)
Ground
W
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
DQ
0
- DQ
7
E
G
V
CC
V
SS
21 August 1998
5-35
STK25CA8
ABSOLUTE MAXIMUM RATINGS
a
Voltage on input relative to V
SS
. . . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Note a:
Stresses greater than those listed under “Absolute Max-
mum Ratings” may cause permanent damage to the
device. This a stress rating only, and functional operation
of the device at conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC1b
I
CC2c
I
CC3b
I
CC4c
I
SBd
I
ILK
I
OLK
V
IH
V
IL
V
OH
PARAMETER
MIN
Average Current
Average Current During STORE
Average V
CC
Current at t
AVAV
= 200ns
Average Current During
AutoStore™
Cycle
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
2.2
V
SS
– .5
2.4
MAX
125
110
20
22
18
9
±2
±10
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
-40
85
MIN
MAX
133
120
25
25
20
9
±2
±10
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
°C
INDUSTRIAL
UNITS
(V
cc
= 5.0V
±
10%)
NOTES
t
AVAV
= 45ns
t
AVAV
= 55ns
All inputs Don’t Care
W
≥
(V
CC
– 0.2V)
All others cycling, CMOS levels
All inputs Don’t Care
E
≥
(V
CC
– 0.2V)
All others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All inputs
All inputs
I
OUT
= – 4mA
I
OUT
= 8mA
SRAM READ CYCLES #1 & SRAM READ
V
OL
Output Logic “0” Voltage
0.4
T
A
Operating Temperature
0
70
Note b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC
and I
CC
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
2
4
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input rise and fall times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and output timing reference levels . . . . . . . . . . . . . . . . . 1.5V
Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input capacitance
Output capacitance
(T
A
= 25
°
C, f = 1.0MHz)
MAX
20
28
UNITS
pF
pF
CONDITIONS
Output
480 Ohms
∆V
= 0 to 3V
∆V
= 0 to 3V
255 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
21 August 1998
5-36
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAVf
t
AVQVg
t
GLQV
t
AXQXg
t
ELQX
t
EHQZh
t
GLQX
t
GHQZh
t
ELICCHe
t
EHICCLd, e
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
0
3
5
45
MIN
STK25CA8
(V
cc
= 5.0V
±
10%)
STK25CA8-45
MAX
45
55
45
20
3
5
15
0
15
0
45
55
25
25
55
320
STK25CA8-55
UNITS
MIN
MAX
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note f: W must be high during SRAM read cycles and low during SRAM write cycles.
Note g: I/O state assumes E, G, < V
IL
and W > V
IH
; device is continuously selected
Note h: Measured + 200mV from steady state output voltage
SRAM READ CYCLE #1 (Address Controlled)
f, g
t
AVAV
ADDRESS
5
t
AXQX
3
2
t
AVQV
DATA VALID
DQ(Data Out)
SRAM READ CYCLE #2 (E Controlled)
f
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
7
6
1
2
t
EHICCL
11
G
t
GLQX
DQ(Data Out)
t
ELICCH
I
CC
STANDBY
10
DATA VALID
8
4
t
GLQV
t
GHQZ
9
ACTIVE
21 August 1998
5-37
STK25CA8
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZh, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
5
PARAMETER
MIN
45
30
30
15
0
30
0
0
15
5
MAX
MIN
55
40
40
12
0
40
0
0
25
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(V
cc
= 5.0V
±
10%)
STK25CA8-45
STK25CA8-55
UNITS
Note i:
Note j:
If W is low when E goes low the outputs remain in the high impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1:
W CONTROLLED
j
t
AVAV
ADDRESS
14
t
ELWH
19
12
t
WHAX
E
t
AVWH
t
AVWL
W
t
WLWH
15
16
13
18
17
t
DVWH
DATA IN
20
t
WLQZ
DATA VALID
t
WHDX
DATA OUT
PREVIOUS DATA
HIGH IMPEDENCE
t
WHQX
21
SRAM WRITE CYCLE #2:
E CONTROLLED
j
t
AVAV
ADDRESS
t
AVEL
E
18
14
19
12
t
ELEH
t
EHAX
t
AVEH
W
t
WLEH
15
13
17
t
DVEH
DATA IN
DATA OUT
HIGH IMPEDENCE
DATA VALID
t
EHDX
16
21 August 1998
5-38
STK25CA8
AutoStore™
/ POWER-UP RECALL
SYMBOLS
NO.
Standard
22
23
24
25
26
t
RESTORE
t
STORE
t
DELAY
V
SWITCH
V
RESET
Power Up RECALL Duration
STORE Cycle Duration
Time allowed to Complete SRAM Cycle
Low Voltage Trigger Level
Low Voltage Reset Level
1
PARAMETER
(V
cc
= 5.0V
±
10%)
STK25CA8
UNITS NOTES
MIN
MAX
550
10
µs
ms
µs
4.5
3.9
V
V
k
g
g
4.0
Note k: t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
AutoStore™
/ POWER UP RECALL
V
25
CC
5V
V
SWITCH
V
RESET
26
AUTOSTORE
TM
t
STORE
POWER UP RECALL
23
22
t
RESTORE
24
t
DELAY
W
DQ
(Data Out)
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
RECALL WHEN
ABOVE V
SWITCH
21 August 1998
5-39
FPGA/CPLD
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