STK25CA8
128K x 8
AutoStore™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM Module
FEATURES
• Nonvolatile Storage without Battery Problems
• Directly Replaces 128K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 35ns and 45ns Access Times
•
STORE
to Nonvolatile Elements Initiated by
AutoStore™
on Power Down
•
RECALL
to SRAM on Power Restore
• 22mA I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
• 32-Pin 600 mil Dual In-Line Module
DESCRIPTION
Preliminary
The Simtek STK25CA8 is a fast static
RAM
with a
nonvolatile element incorporated in each static
memory cell. The
SRAM
can be read and written an
unlimited number of times, while independent non-
volatile data resides in the Nonvolatile Elements.
Data transfers from the
SRAM
to the Nonvolatile Ele-
ments (the
STORE
operation) can take place auto-
matically on power down using charge stored in
system capacitance. Transfers from the Nonvolatile
Elements to the
SRAM
(the
RECALL
operation) take
place automatically on restoration of power.
BLOCK DIAGRAM
A
15
A
16
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
MODULE
DECODER
QUANTUM TRAP
512 x 512
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
STORE/
RECALL
CONTROL
PIN CONFIGURATIONS
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
POWER
CONTROL
V
CC
A
15
NC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
ROW DECODER
32 - 600 mil
Dual In-Line
Module
PIN NAMES
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
- A
16
W
DQ
0
- DQ
7
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
E
G
E
W
G
V
CC
V
SS
January 2003
1
Document Control # ML0021 rev 0.0
STK25CA8
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL
I
CC
b
1
(V
CC
= 5.0V
±
10%)
COMMERCIAL
MIN
MAX
140
125
20
22
18
9
±2
±10
2.2
V
SS
– .5
2.4
0.4
0
70
– 40
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
85
INDUSTRIAL
MIN
MAX
150
133
25
25
20
9
±2
±10
V
CC
+ .5
0.8
UNITS
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
°C
t
AVAV
= 35ns
t
AVAV
= 45ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA
I
OUT
= 8mA
NOTES
PARAMETER
Average V
CC
Current
Average V
CC
Current During
STORE
Average V
CC
Current at t
AVAV
= 200ns
Average V
CC
Current During
AutoStore™
Cycle
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
I
CC
c
2
3
I
CC
b
I
CC
c
4
I
SB
d
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
Note c: I
CC
and I
CC
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
4
Note d: E
≥
2
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
OUTPUT
255 Ohms
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25
°
C, f = 1.0MHz)
MAX
20
28
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
30 pF
INCLUDING
SCOPE
AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
January 2003
2
Document Control # ML0021 rev 0.0
STK25CA8
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
#1, #2
t
ELQV
t
AVAV
f
g
(V
CC
= 5.0V
±
10%)
PARAMETER
STK25CA8-35
MIN
MAX
35
35
35
15
5
5
13
0
13
0
35
0
45
0
15
5
5
15
45
45
20
STK25CA8-45
MIN
MAX
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
Chip Enable Access Time
Read Cycle Time
Address Access Time
t
AVQV
t
GLQV
t
AXQX
t
ELQX
t
EHQZ
h
t
GLQX
t
GHQZ
h
e
d, e
g
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
OHZ
t
PA
t
PS
t
ELICCH
t
EHICCL
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G, < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
f, g
t
AVAV
ADDRESS
t
AXQX
DQ (DATA OUT)
5
3
2
t
AVQV
DATA VALID
SRAM READ CYCLE #2:
E Controlled
f
t
AVAV
ADDRESS
t
ELQV
E
6
t
ELQX
1
1
1
2
t
EHICCL
7
t
EHQZ
G
8
4
t
GLQV
t
GHQZ
9
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
DATA VALID
I
CC
STANDBY
January 2003
3
Document Control # ML0021 rev 0.0
STK25CA8
SRAM WRITE CYCLES #1 & #2
NO.
12
13
14
15
16
17
18
19
20
21
SYMBOLS
#1
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
h, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
MIN
35
25
25
12
0
25
0
0
13
5
(V
CC
= 5.0V
±
10%)
STK25CA8-35
MAX
STK25CA8-45
MIN
45
30
30
15
0
30
0
0
15
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1:
W Controlled
j
t
AVAV
ADDRESS
t
ELWH
E
14
1
9
12
t
WHAX
t
AVWL
W
18
t
AVWH
t
WLWH
15
16
13
17
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
20
DATA VALID
t
WHDX
t
WHQX
21
SRAM WRITE CYCLE #2:
E Controlled
j
t
AVAV
ADDRESS
t
AVEL
E
18
1
4
19
12
t
ELEH
t
EHAX
t
AVEH
W
t
WLEH
15
16
13
1
7
t
DVEH
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
t
EHDX
January 2003
4
Document Control # ML0021 rev 0.0
STK25CA8
AutoStore™/POWER-UP RECALL
NO.
22
23
24
25
26
SYMBOLS
Standard
t
RESTORE
t
STORE
t
DELAY
V
SWITCH
V
RESET
Power-up
RECALL
Duration
STORE
Cycle Duration
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
Low Voltage Reset Level
1
4.0
4.5
3.9
PARAMETER
(V
CC
= 5.0V ± 10%)
STK25CA8
MIN
MAX
550
10
UNITS
µs
ms
µs
V
V
NOTES
k
g
g
Note k: t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
AutoStore™/POWER-UP RECALL
V
CC
5V
25
V
SWITCH
26
V
RESET
AutoStore™
23
t
STORE
24
t
DELAY
POWER-UP
RECALL
t
RESTORE
W
DQ (DATA OUT)
22
POWER-UP
RECALL
BROWN OUT
NO
STORE
DUE TO
NO SRAM WRITES
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
RECALL
WHEN
V
CC
RETURNS
ABOVE V
SWITCH
January 2003
5
Document Control # ML0021 rev 0.0
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