Integrated
Passive Components
Balanced Line EMI Chip
BLC
The Syfer Balanced Line Chip is a 3 terminal EMI chip device. The
revolutionary design provides simultaneous line-to-line and line-to-
ground filtering, using a single ceramic chip. In this way, differential
and common mode filtering are provided in one device. Capable of
replacing 2 or more conventional devices, it is ideal for balanced lines,
twisted pairs and dc motors, in automotive, audio, sensor and other
applications.
These filters can prove invaluable in meeting stringent EMC demands
particularly in automotive applications.
Specifications
Dielectric
Electrical Configuration
Capacitance Measurement
Typical Capacitance Matching
Temperature Rating
Dielectric Withstand Volage
Insulation Resistance
Termination Material
X7R or C0G
Multiple capacitance
At 1000hr point
Better than 5%
-55°C to 125°C
2.5 x Rated Volts for 5 secs.
Charging current limited to 50mA Max.
10,000 Mohms Min
Nickel Barrier
L
T
Advantages
●
Replaces 2 or 3 capacitors with one device
●
Matched capacitance line to ground on both lines
●
Low inductance due to cancellation effect
●
Capacitance line to line
●
Differential and common mode attenuation
●
Effects of temperature and voltage variation eliminated
●
Effect of ageing equal on both lines
●
High current capability
W
L1
L2
INPUT 1
A
C1
GROUND
C1
C2
A
Applications
●
Balanced lines
●
Twisted pairs
●
EMI Suppression on DC motors
●
Sensor/transducer applications
●
Wireless communications
●
Audio
INPUT 2
B
B
Chip
Size
0603*
0805
1206
1410
1812
2220
L
1.6±0.2 (0.063±0.008)
2.0±0.3 (0.08±0.012)
3.2±0.3 (0.126±0.012)
3.6±0.3 (0.14±0.012)
4.5±0.35 (0.18±0.14)
5.7±0.4 (0.22±0.016)
W
0.8±0.2 (0.03±0.008)
1.25±0.2 (0.05±0.008)
1.60±0.2 (0.063±0.008)
2.5±0.3 (0.1±0.012)
3.2±0.3 (0.126±0.012)
5.0±0.4 (0.2±0.016)
T
0.5±0.15 (0.02±0.006)
1.0±0.15 (0.04±0.006)
1.1±0.2 (0.43±0.008)
2 max. (0.08 max.)
2 max. (0.08 max.)
2.5 max. (0.1 max.)
L1
0.3±0.2 (0.012±0.008)
0.5±0.25 (0.02±0.01)
0.95±0.3 (0.037±0.012)
1.20±0.3 (0.047±0.012)
1.5±0.35 (0.6±0.14)
2.25±0.4 (0.09±0.016)
L2
0.2±0.1 (0.008±0.004)
0.3±0.15 (0.012±0.006)
0.5±0.25 (0.02±0.01)
0.5±0.25 (0.02±0.01)
0.5±0.25 (0.02±0.01)
0.75±0.25 (0.03±0.01)
Recommended Solder Lands
B
C
A
Insertion Loss Characteristics (common mode)
Typical 50 ohm system
80
220nF
4.7nF
2.2nF
1nF
470pF
220pF
100pF
47pF
22pF
100nF
47nF
22nF
40
10nF
D
Chip Size
0603*
0805
1206
1410
1812
2220
A
0.6 (0.024)
0.95 (0.037)
1.2 (0.047)
2.05 (0.08)
2.65 (0.104)
4.15 (0.163)
Dimensions
B
0.6 (0.024)
0.9 (0.035)
0.9 (0.035)
1.0 (0.04)
1.4 (0.055)
1.4 (0.055)
mm (inches)
C
D
0.4 (0.016) 0.2 (0.008)
0.3 (0.012) 0.4 (0.016)
0.6 (0.024) 0.8 (0.03)
0.7 (0.028) 0.9 (0.035)
0.8 (0.03) 1.4 (0.055)
1.2 (0.047) 1.8 (0.071)
Insertion Loss (dB)
60
20
0
0.1
1
10
100
1000
Frequency (MHz)
notes
1. For details of ordering see page 62
2. For soldering and installation information see page 69
*
The 0603 chip size is a development item that will be available during the life
of this catalogue. All technical information should be considered provisional
and subject to change.
59
Integrated
Passive Components
Balanced Line EMI Chip
BLC
12
14
22
08
18
06
10
20
05
12
3
100V
*0
e
alu
pV
Ca C1 %)
20
(±
e
alu
pV
Ca C2 %)
20
(±
X7R
X7R
100V
C0G
X7R
X7R
C0G
X7R
100V
C0G
C0G
C0G
1000
4000
Voltage
100V
50V
25V
16V
Reeled
Quantity
178mm (7”)
330mm (13”)
4000
16000
3000
12000
2500
10000
2000
8000
60
notes
1. For detail of ordering see page 62.
*
The 0603 chip size is a development item that will be available during the life
of this catalogue. All technical information should be considered provisional
and subject to change.
C0G
1000
4000
X7R
100V
e
od
pC
Ca
60
100
120
150
180
220
270
330
390
470
560
680
820
101
121
151
181
221
271
331
391
471
561
681
821
102
122
152
182
222
272
332
392
472
562
682
822
103
123
153
183
223
273
333
393
473
563
683
823
104
124
154
184
224
274
334
394
474
564
684
824
105
125
10pF
12
15
18
22
27
33
39
47
56
68
82
100
120
150
180
220
270
330
390
470
560
680
820
1.0nF
1.2
1.5
1.8
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
10
12
15
18
22
27
33
39
47
56
68
82
100
120
150
180
220
270
330
390
470
560
680
820
1µF
1.2
5pF
6
7.5
9
11
13.5
16.5
19.5
23.5
28
34
41
50
60
75
90
110
135
165
195
235
280
340
410
0.5nF
0.6
0.75
0.9
1.1
1.35
1.65
1.95
2.35
2.8
3.4
4.1
5
6
7.5
9
11
13.5
16.5
19.5
23.5
28
34
41
50
60
75
90
110
135
165
195
235
280
340
410
0.5µF
0.6
50V
50V
100V
100V
100V
100V
100V
100V
Integrated
Passive Components
Balanced Line EMI Chip
BLC
The Syfer Balanced Line EMI chip has a unique internal architecture
which provides unbeatable EMC performance for dual line data
transmission.
A typical application for dual line data transmission would see a
board layout using decoupling chip capacitors or 3 terminal
feedthrough chips as shown in Fig 1.
INPUT 1
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 4
CHIP CAPACITORS
Fig 1
The Balanced Line EMI chip replaces decoupling capacitors or 3
terminal feedthrough chips on a 1 for 2 basis and provides line to
line (differential mode) decoupling. Fig 2.
C1
EARTH
TRACKS
INPUT 2
INPUT 3
EARTH
TRACKS
3 TERMINAL CHIPS
LINE A
C2
INPUT 1
INPUT 2
INPUT 3
INPUT 4
BALANCED LINE
EMI CHIP
Fig 2
The internal structure furnishes a reduced inductance when
compared to that of a conventional capacitor. This is a result of the
novel internal electrode structure which inherently reduces the
inductance by the cancellation effect of opposing currents in close
proximity.
The capacitance line to ground (common mode) is closely matched
due to the symmetry within the design. As the device includes line
to ground capacitance for both lines, any temperature, ageing and
voltage effects will have an equal influence on both lines therefore
maintaining balanced decoupling.
The construction also allows a capacitance between lines as well as
to ground as shown in Fig 3.
LINE B
EARTH
TRACKS
C1
Fig 3
C2, the line to line capacitance, is half the line to ground
capacitance thus providing coupling of high frequency interference
between balanced lines.
Because the part acts as a decoupling device, the current limitations
of a standard 3 terminal chip do not apply. The single line 3
terminal feedthrough chip carries the signal current through the
very thin feedthrough electrodes within the device which have
limited DC resistance and so can cause excessive heating, hence the
maximum permissible current is often limited to around 300 mA for
a 1206 device. The dual line 3 terminal chip is in by-pass across
two lines and so is unaffected by high signal currents.
Table 1 offers a comparison of decoupling devices and
demonstrates how the Balanced Line EMI chip extends the options
for EMC circuit protection.
Component
Chip capacitor
3 terminal
feedthrough
Advantages
●
Industry standard
●
Feedthrough
●
Lower Inductance
●
Very low inductance
●
Replaces 2 (or 3) components
●
Negates the effects of
temperature, voltage and ageing
●
Provides both common mode and
differential mode attenuation
Disadvantages
●
Requires 1 per line
●
High inductance
●
Capacitance matching problems
●
Current limited
Applications
●
By-pass
●
Low frequency
●
Feedthrough
●
Unbalanced lines
●
High frequency
●
By-pass
●
Balanced lines
●
High frequency
●
DC electric motors
Balanced line
EMI chip
●
Not for unbalanced signal lines
Table 1
61
Integrated
Passive Components
Balanced Line EMI Chip
BLC
Application Note
One of the significant features of this product is its extremely low
inductance, making it particularly suitable for high speed digital
applications and for reduction of common mode currents for power
line applications. Inductance cancellation, due to the effect of
opposing current flow across the device, results in a typical line to
line inductance of around 100pH, with a corresponding line to
ground inductance of 50pH.
The Balanced Line EMI chip satisfies the need for high speed
communications systems using balanced lines or twisted pairs
offering low inductance (therefore high frequency operation),
reduced board space, reduced component count and an
unparalleled performance.
Ordering Information
1206
Chip Size
Reference
J
Termination
J = Nickel
Barrier
100
Voltage
016 = 16 volts
025 = 25 volts
050 = 50 volts
100 = 100 volts
0222
Capacitance
Expressed in picofarads (pF).
First digit is 0.
Second and third digits are significant
figures of capacitance code.
The fourth digit is number of zeros
following.
Example: 0222=2200pF.
M
Tolerance
M= ±20%
X
Dielectric
C = C0G
X = X7R
T
Packaging
T =178mm
(7”) reel
R =330mm
(13”) reel
B =Bulk
E03
Balanced Line
EMI Chip
●
Syfer Technology are able to provide comprehensive applications
and design in support.
●
Technical and application papers are available on request from
the Sales Office.
Manufactured in the UK by Syfer Technology Limited under licence from X2Y attenuators LLC.
62
FPGA/CPLD
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