240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb
version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width
form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchro-
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-
0.1V Power Supply
All inputs and outputs are compatible with
SSTL_1.8 interface
8 Bank architecture
Posted CAS
Programmable CAS Latency 3, 4, 5, 6
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
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•
•
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•
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both
sequential and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60 ball(x4/x8)
133.35 x 30.00 mm form factor
RoHS compliant
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ORDERING INFORMATION
Part Name
HYMP112P72CP8-C4/Y5/S6/S5
HYMP125P72CP8-C4/Y5/S6/S5
HYMP125P72CP4-C4/Y5/S6/S5
HYMP151P72CP8-C4/Y5/S6/S5
HYMP151P72CP4-C4/Y5/S6/S5
HYMP31GP72CMP4-C4/Y5
HYMP112R72CP8-E3/C4
HYMP125R72CP4-E3/C4
HYMP151R72CP4-E3/C4
Density
1GB
2GB
2GB
4GB
4GB
8GB
1GB
2GB
4GB
Organization
128Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
128Mx72
256Mx72
512Mx72
# of
DRAMs
9
18
18
36
36
72
9
18
36
# of
ranks
1
2
1
4
2
4
1
1
2
Parity
Support
O
O
O
O
O
O
X
X
X
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.7 / Jun. 2009
1
1
240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol
CK0
Type
IN
Polarity
Positive
Edge
Negative
Edge
Active High
Pin Description
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0
IN
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CKE[1:0]
IN
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
ing the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
On-Die Termination signals.
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the
command being entered.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current
DDR2 unbuffered DIMM designs, V
DDQ
shares the same power plane as V
DD
pins.
S[1:0]
IN
Active Low
ODT[1:0]
RAS, CAS, WE
Vref
V
DDQ
BA[2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
Selects which DDR2 SDRAM internal bank of Eight is activated.
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autopre-
charge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is dis-
abled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
A[9:0],A10/AP
A[13:11]
IN
-
DQ[63:0],
CB[7:0]
IN
-
DM[8:0]
IN
Active High
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with
that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. V
DD
and V
DDQ
pins are tied to
V
DD
/V
DDQ
planes on these modules.
V
DD
,V
SS
Supply
Positive
Edge
Negative
Edge
-
DQS[17:0]
I/O
Positive line of the differential data strobe for input and output data
DQS[17:0]
I/O
Negative line of the differential data strobe for input and output data
SA[2:0]
IN
These signals are tied at the system planar to either V
SS
or V
DDSPD
to configure the serial SPD
EEPROM address range.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be con-
nected from the SDA bus line to V
DDSPD
on the system planar to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from
SCL to V
DDSPD
to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM
supply is operable from 1.7V to 3.6V.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all
register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low
level (the PLL will remain synchronized with the input clock)
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
SDA
I/O
-
SCL
IN
-
VDDSPD
Supply
RESET
IN
Par_In
Err_Out
TEST
IN
OUT
Rev. 0.7 / Jun. 2009
3
1
240pin Registered DDR2 SDRAM DIMMs
PIN DESCRIPTION
Pin
CK0
CK0
CKE0~CKE1
RAS
CAS
WE
S0,S1
A0~A9,A11~A13
A10/AP
BA0, BA1, BA2
SCL
SDA
SA0~SA2
Par_In
Err_Out
RESET
CB0~CB7
Pin Description
Clock Input, positive line
Clock input, negative line
Clock Enable Input
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select Input
Address input
Address input/Autoprecharge
SDRAM Bank Address
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
E
2
PROM Address Inputs
Parity bit for the Address and Control bus
Parity error found on the Addre
Reset Enable
Data Strobe Inputs/Outputs
Pin
ODT[1:0]
VDDQ
DQ0~DQ63
CB0~CB7
DQS(0~8)
DQS(0~8)
DM(0~8),DQS(9~17)
DQS(9~17)
RFU
NC
TEST
VDD
VDDQ
VSS
VREF
VDDSPD
Pin Description
On Die Termination Inputs
DQs Power Supply
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Maskes/Data strobes
Data strobes, negative line
Reserved for Future Use
No Connect
Memory bus test tool (Not Connected and Not
Usable on DIMMs)
Core Power
I/O Power Supply
Ground
Reference Power Supply
Power Supply for SPD
PIN LOCATION
pin #1
Front Side
Pin #64
Pin #65
Pin #120
Pin #121
Back Side
Pin #184
Pin #185
pin #240
Rev. 0.7 / Jun. 2009
4
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