TMP320C50KGD, TMP320LC50KGD
DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIE
SGZS008C -- JULY 1996 -- REVISED JUNE 2000
D
25-ns, 35-ns, and 50-ns Single-Cycle
D
D
D
D
D
D
Instruction Execution Time for 5-V
Operation
50-ns Single-Cycle Instruction Execution
Time for 3.3-V Operation
Source-Code Compatible With All ’C1x and
’C2x Devices
RAM-Based Operation
- 9K-Word
×
16-Bit Single-Access On-Chip
-
Program/Data RAM
- 1056-Word
×
16-Bit Dual-Access On-Chip
-
Data RAM
2K-Word
×
16-Bit On-Chip Boot ROM
224K-Word
×
16-Bit Maximum Addressable
External Memory Space (64K-Word
Program, 64K-Word Data, 64K-Word I/O,
and 32K-Word Global)
32-Bit Arithmetic Logic Unit (ALU)
- 32-Bit Accumulator (ACC)
-
- 32-Bit Accumulator Buffer (ACCB)
-
D
D
D
D
D
D
D
D
D
D
D
D
16-Bit Parallel Logic Unit (PLU)
16
×
16-Bit Multiplier, 32-Bit Product
Eleven Context Switch Registers
Two Buffers for Circular Addressing
Full-Duplex Synchronous Serial Port
Time-Division Multiplexed Serial Port (TDM)
Timer With Control and Counter Registers
Sixteen Software-Programmable Wait-State
Generators
Divide-By-1 Clock Option
IEEE Standard 1149.1
†
Test Access Port
Operations are Fully Static
Fabricated Using the Texas Instruments (TI)
Enhanced Performance Implanted CMOS
(EPIC™) 0.64-μm Technology
description
The TMP320C50KGD digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor
manufactured in 0.64-μm double-level metal CMOS technology. The TMP320LC50KGD has the same
functionality as the ’C50KGD except for operation at 3.3 V instead of 5 V.
Texas Instruments Military Products currently employs three primary processes for the development of a known
good die (KGD), one of which is applied to the TMP320C50 and TMP320LC50 devices. This process, known
as hot-chuck-probe, uses a standard probed product that is tested again, this time at full data sheet
specifications, in wafer form at speed and elevated temperature (85°C). Each individual die then is sawed,
inspected, and packed for shipment. This flow produces a bare die that has been temperature-tested at speed
and is known to be good, without having to use a temporary package.
A number of enhancements to the basic ’C2x architecture give the ’C5x a minimum 2x performance over the
previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to
subroutine, and delayed return from subroutine, allows the ’C5x to perform instructions in fewer cycles. The
addition of a PLU gives the ’C5x a method of manipulating bits in data memory without using the ACC and ALU.
The ’C5x has additional shifting and scaling capability for proper alignment of multiplicands or storage of values
to data memory.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1--1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
EPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251--1443
1
SGZS008C -- JULY 1996 -- REVISED JUNE 2000
TMP320C50KGD, TMP320LC50KGD
DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIE
description (continued)
With the addition of the IDLE2 instruction, the ’C5x achieves low-power consumption. IDLE2 removes the
functional clock from the internal hardware of the ’C5x that puts it into a total-sleep mode using only 5
μA.
A low-logic level on an external interrupt with chip duration of at least five clock cycles ends the IDLE2 mode.
TMP PRODUCT FLOW; 40 AND 57 MHz
Multiprobe
Test conditions
DC test
AC test
Visual
Warranty
dc test @ 25°C
Per commercial data sheet
Hot chuck probe @ 85°C
Hot chuck probe @ 85°C @ Speed
40x
Datasheet upon shipment, 1 year
For electrical and timing specifications, see the
TMS320C5x, TMS320LC5x Digital Signal Processors
data
sheet (literature number SPRS030).
SPECIFIC DIE-RELATED INFORMATION
Die Size (approximate)
Die Thickness
Backside Surface Finish
Die Backside Potential
Max Allowable Die Junction Operating Temperature
Glassivation Material and Thickness
Recommended Packing
Die Attach Information
Suggested Bond Wire Size
Suggested Bonding Method
ESD Sensitivity
Max Allowable Process Temperature for Die Attach
358 mils x 338 mils
11 mils
1 mil
SIO2
Floating
125°C
3KAOX/9KACN
GEL PAK
SILVER GLASS
1.25 AL
WEDGE
Class II
450°C
2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251--1443
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