M67025E
8 K
16 CMOS Dual Port RAM Rad Tolerant
Introduction
The M67025E is a very low power CMOS dual port static
RAM organised as 8192
×
16. The M67025E is designed
to be used as a stand-alone 16 bit dual port RAM or as a
combination MASTER/SLAVE dual port for 32 bit or
more width systems. The TEMIC MASTER/SLAVE dual
port approach in memory system applications results in
full speed, error free operation without the need of an
additional discrete logic.
Master and slave devices provide two independant ports
with separate control, address and I/O pins that permit
independant, asynchronous access for reads and writes to
any location in the memory. An automatic power down
feature controlled by CS permits the on-chip circuitry of
each port in order to enter a very low stand by power
mode.
Using an array of eight transistors (8T) memory cell, the
M67025E combines an extremely low standby supply
current (typ = 1.0
µA)
with a fast access time at 30 ns
over the full temperature range. All versions offer battery
backup data retention capability with a typical power
consumption at less than 5
µW.
The M67025E is processed according to the methods of
the latest revision of the MIL STD 883 (class B or S), ESA
SCC 9000 or QML.
Features
D
Fast access time : 30, 45 ns
D
Wide temperature range :
–55
°C
to +125
°C
D
Separate upper byte and lower byte control for multiplexed
bus compatibility
D
Expandable data bus to 32 bits or more using master/slave
chip select when using more than one device
D
On chip arbitration logic
D
Versatile pin select for master or slave :
– M/S = H for busy output flag on master
– M/S = L for busy input flag on slave
D
INT flag for port to port communication
D
Full hardware support of semaphore signaling between ports
D
Fully asynchronous operation from either port
D
Battery back-up operation : 2 V data retention
D
TTL compatible
D
Single 5 V
±
10 % power supply
Rev. F – June 30, 1999
1
M67025E
Interface
Block Diagram
Note :
1. (MASTER) : BUSY is output. (SLAVE) : BUSY is input.
2. LB = Lower Byte
UB = Upper Byte
Pin Names
LEFT PORT
CS
L
R/W
L
OE
L
A
0L – 12L
I/O
0L – 15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/S
Vcc
GND
RIGHT PORT
CS
R
R/W
R
OE
R
A
0R – 12R
I/O
0R – 15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
NAMES
Chip select
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2
Rev. F – June 30, 1999
M67025E
Functional Description
Pin Configuration
SEM
L
I/O
2L
R/W
L
I/O
7L
I/O
4L
I/O
3L
I/O
0L
OE
L
I/O
6L
I/O
5L
GND
I/O
1L
A
9L
A
8L
Vcc
INDEX
A
10L
LB
L
A
12L
A
11L
CE
L
UB
L
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
Vcc
GND
I/O
0R
I/O
1R
I/O
2R
Vcc
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
1
63
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
67025
84-PIN MQFPF
TOP VIEW
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
21
43
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
I/O
9R
I/O
10R
UB
R
LB
R
A
12R
A
11R
CE
R
I/O
12R
I/O
13R
SEM
R
A
10R
GND
I/O
11R
I/O
14R
GND
I/O
15R
OE
R
R/W
R
A
8R
A
7R
A
9R
Rev. F – June 30, 1999
3
M67025E
Functional Description
The M67025E has two ports with separate control,
address and I/0 pins that permit independent read/write
access to any memory location. These devices have an
automatic power-down feature controlled by CS.CS
controls on-chip power-down circuitry which causes the
port concerned to go into stand-by mode when not
selected (CS high). When a port is selected access to the
full memory array is permitted. Each port has its own
Output Enable control (OE). In read mode, the port’s OE
turns the Output drivers on when set LOW.
Non-conflicting
READ/WRITE
conditions
are
illustrated in table 1.
The interrupt flag (INT) allows communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
is assigned to each port. The left port interrupt flag (INT
L
)
is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading
address location 1FFE. Similarly, the right port interrupt
flag (INT
R
) is set when the left port writes to memory
location 1FFF (HEX), and the right port must read
memory location 1FFF in order to clear the interrupt flag
(INT
R
). The 16 bit message at 1FFE or 1FFF is
user-defined. If the interrupt function is not used, address
locations 1FFE and 1FFF are not reserved for mail boxes
but become part of the RAM. See table 3 for the interrupt
function.
if the CSs are low before an address match, on-chip
control logic arbitrates between the left and right
addresses for access (refer to table 4). The inhibited port’s
BUSY flag is set and will reset when the port granted
access completes its operation in both arbitration modes.
Data Bus Width Expansion
Master/Slave Description
Expanding the data bus width to 32 or more bits in a
dual-port RAM system means that several chips may be
active simultaneously. If every chips has a hardware
arbitrator, and the addresses for each arrive at the same
time one chip may activate in L BUSY signal while
another activates its R BUSY signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
To overcome this “Busy Lock-Out” problem, MHS has
developped a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to the
MASTER with no external components, giving a speed
advantage over other systems.
When dual-port RAMs are expanded in width, the
SLAVE RAMs must be prevented from writing until after
the BUSY input has settled. Otherwise, the SLAVE chip
may begin a write cycle during a conflict situation.
Conversely, the write pulse must extend a hold time
beyond BUSY to ensure that a write cycle occurs once the
conflict is resolved. This timing is inherent in all
dual-port memory systems where more than one chip is
active at the same time.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
Arbitration Logic
Functional Description
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns determine
which port has access. In all cases, an active BUSY flag
will be set for the inhibited port.
The BUSY flags are required when both ports attempt to
access the same location simultaneously. Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the
inhibited port. BUSY is set at speeds that allow the
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
A conflict will occur when both left and right ports are
active and the two addresses coincide. The on-chip
arbitration determines access in these circumstances.
Two modes of arbitration are provided : (1) if the
addresses match and are valid before CS on-chip control
logic arbitrates between CS
L
and CS
R
for access ; or (2)
Semaphore Logic
Functional Description
The M67025E is an extremely fast dual-port 4k
×
16
CMOS static RAM with an additional locations dedicated
to binary semaphore flags. These flags allow either of the
processors on the left or right side of the dual-port RAM
to claim priority over the other for functions defined by
the system software. For example, the semaphore flag can
be used by oner processor to inhibit the other from
accessing a portion of the dual-port RAM or any other
shared resource.
4
Rev. F – June 30, 1999
M67025E
The dual-port RAM has a fast access time, and the two
ports are completely independent of each another. This
means that the activity on the left port cannot slow the
access time of the right port. The ports are identical in
function to standard CMOS static RAMs and can be read
from, or written to, at the same time with the only possible
conflict arising from simultaneous writing to, or a
simultaneous READ/WRITE operation on, a
non-semaphore location. Semaphores are protected
against such ambiguous situations and may be used by the
system program to prevent conflicts in the
non-semaphore segment of the dual-port RAM. The
devices have an automatic power-down feature
controlled by CS, the dual-port RAM select and SEM, the
semaphore enable. The CS and SEM pins control
on-chip-power-down circuitry that permits the port
concerned to go into stand-by mode when not selected.
This conditions is shown in table 1 where CS and SEM
are both high.
Systems best able to exploit the M67025E are based
around multiple processors or controllers and are
typically very high-speed, software controlled or
software-intensive systems. These systems can benefit
from the performance enhancement offered by the
M 67025 hardware semaphores, which provide a lock-out
mechanism without the need for complex programming.
Software handshaking between processors offers the
maximum level of system flexibility by permitting shared
resources to be allocated in varying configurations. The
M67025E does not use its semaphore flags to control any
resources through hardware, thus allowing the system
designer total flexibility in system architecture.
An advantage of using semaphores rather than the more
usual methods of hardware arbitration is that neither
processor ever incurs wait states. This can prove to be a
considerable advantage in very high speed systems.
reading it. If the latch has been set the processor assumes
control over the shared resource. If the latch has not been
set, the left processor has established that the right
processor had set the latch first, has the token and is using
the shared resource. The left processor may then either
repeatedly query the status of the semaphore, or abandon
its request for the token and perform another operation
whilst occasionally attempting to gain control of the
token through a set and test operation. Once the right side
has relinquished the token the left side will be able to take
control of the shared resource.
The semaphore flags are active low. A token is requested
by writing a zero to a semaphore latch, and is relinquished
again when the same side writes a one to the latch.
The eight semaphore flags are located in a separate
memory space from the dual-port RAM in the M67025E.
The address space is accessed by placing a low input on
the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins
(address, OE and R/W) as normally used in accessing a
standard static RAM. Each of the flags has a unique
address accessed by either side through address pins
A0-A2. None of the other address pins has any effect
when accessing the semaphores. Only data pin D
0
is used
when writing to a semaphore. If a low level is written to
an unused semaphore location, the flag will be set to zero
on that side and to one on the other side (see table 5). The
semaphore can now only be modified by the side showing
the zero. Once a one is writen to this location from the
same side, the flag will be set to one for both sides (unless
a request is pending from the other side) and the
semaphore can then be written to by either side.
The effect the side writing a zero to a semaphore location
has of locking out the other side is the reason for the use
of semaphore logic in interprocessor communication. (A
thorough discussion of the use of this feature follows
below). A zero written to the semaphore location from the
locked-out side will be stored in the semaphore request
latch for that side until the semaphore is relinquished by
the side having control. When a semaphore flag is read its
value is distributed to all data bits so that a flag set at one
reads as one in all data bits and a flag set at zero reads as
all zeros. The read value is latched into the output register
of one side when its semaphore select (SEM) and output
enable (OE) signals go active. This prevents the
semaphore changing state in the middle of a read cycle as
a result of a write issued by the other side. Because of this
latch, a repeated read of a semaphore flag in a test loop
must cause either signal (SEM or OE) to go inactive,
otherwise the output will never change.
How The Semaphore Flags Work
The semaphore logic is a set of eight latches independent
of the dual-port RAM. These latches can be used to pass
a flag or token, from one port to the other to indicate that
a shared resource is in use. The semaphore provide the
hardware context for the “Token Passing Allocation”
method of use assignment. This method uses the state of
a semaphore latch as a token indicating that a shared
resource is in use. If the left processor needs to use a
resource, it requests the token by setting the latch. The
processor then verifies that the latch has been set by
Rev. F – June 30, 1999
5
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