CY7C185
64-Kbit (8 K × 8) Static RAM
Features
■
Functional Description
The CY7C185
[1]
is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), and active LOW output enable (OE) and
tri-state drivers. This device has an automatic power-down
feature (CE
1
or CE
2
), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
1
and WE
inputs are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address pins
(A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on the
eight data input or output pins.
The input or output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH. A die coat is used to insure alpha immunity.
For a complete list of related documentation,
click here.
High speed
❐
15 ns
Fast t
DOE
Low active power
❐
715 mW
Low standby power
❐
85 mW
CMOS for optimum speed/power
Easy memory expansion with CE
1
, CE
2
and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin
(300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded
DIP
■
■
■
■
■
■
■
■
Logic Block Diagram
I/O
0
INPUT BUFFER
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
CE
1
CE
2
WE
OE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
8K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
SENSE AMPS
I/O
7
A
10
A
11
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com.
A
12
A
0
A
9
Cypress Semiconductor Corporation
Document Number: 38-05043 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 26, 2014
CY7C185
Contents
Pin Configuration ............................................................. 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
AC Test Loads and Waveforms ....................................... 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 7
Typical DC and AC Characteristics .............................. 10
Truth Table ...................................................................... 11
Address Designators ..................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 38-05043 Rev. *G
Page 2 of 18
CY7C185
Pin Configuration
Figure 1. 28-pin DIP / SOJ pinout (Top View)
DIP/SOJ
Top View
NC
A
4
A
5
A
6
A
7
A
8
A9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
Selection Guide
Description
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
-15
15
130
15
-20
20
110
15
-35
35
100
15
Document Number: 38-05043 Rev. *G
Page 3 of 18
CY7C185
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied .......................................... –55
C
to +125
C
Supply voltage to ground potential ..............–0.5 V to +7.0 V
DC voltage applied to outputs
in High Z State
[2]
.........................................–0.5 V to +7.0 V
DC input voltage
[2]
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... >2001 V
Latch-up current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0 °C to +70 °C
–40 °C to +85 °C
V
CC
5 V
10%
5 V
10%
......................................–0.5 V to +7.0 V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply
Current
Automatic Power-down
Current
GND
V
I
V
CC
GND
V
I
V
CC
,
Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA
Max. V
CC
,
CE
1
V
IH
or CE
2
V
IL
,
Min. Duty Cycle =100%
I
SB2
Automatic Power-down
Current
Max. V
CC
,
CE
1
V
CC
– 0.3 V or
CE
2
0.3 V,
V
IN
V
CC
– 0.3 V or
V
IN
0.3 V
–
15
–
15
–
15
mA
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
-15
Min
2.4
–
2.2
–0.5
–5
–5
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+5
+5
130
40
Min
2.4
–
2.2
–0.5
–5
–5
–
–
-20
Max
–
0.4
V
CC
+ 0.3
0.8
+5
+5
110
20
Min
2.4
–
2.2
–0.5
–5
–5
–
–
-35
Max
–
0.4
V
CC
+ 0.3
0.8
+5
+5
100
20
Unit
V
V
V
V
A
A
mA
mA
Note
2. Minimum voltage is equal to –3.0 V for pulse durations less than 30 ns.
Document Number: 38-05043 Rev. *G
Page 4 of 18
CY7C185
Capacitance
Parameter
[3]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz, V
CC
= 5.0 V
Max
7
7
Unit
pF
pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1 481
5V
OUTPUT
5 pF
INCLUDING
JIGAND
SCOPE
R1 481
3.0 V
R2
255
GND
10%
ALL INPUT PULSES
90%
90%
10%
5 ns
THÉVENIN EQUIVALENT
167
1.73 V
R2
255
5 ns
Equivalent to:
OUTPUT
(a)
(b)
Note
3. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05043 Rev. *G
Page 5 of 18
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