CMOS STATIC RAM
256K (32K x 8-BIT)
Integrated Device Technology, Inc.
IDT71256S
IDT71256L
FEATURES:
• High-speed address/chip select time
— Military: 25/30/35/45/55/70/85/100/120/150ns (max.)
— Commercial: 20/25/35/45ns (max.) Low Power only.
• Low-power operation
• Battery Backup operation — 2V data retention
• Produced with advanced high-performance CMOS
technology
• Input and output directly TTL-compatible
• Available in standard 28-pin (300 or 600 mil) ceramic
DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ
and 32-pin LCC
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT71256 is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology.
Address access times as fast as 20ns are available with
power consumption of only 350mW (typ.). The circuit also
offers a reduced power standby mode. When
CS
goes HIGH,
the circuit will automatically go to, and remain in, a low-power
standby mode as long as
CS
remains HIGH. In the full standby
mode, the low-power device consumes less than 15µW,
typically. This capability provides significant system level
power and cooling savings. The low-power (L) version also
offers a battery backup data retention capability where the
circuit typically consumes only 5µW when operating off a 2V
battery.
The lDT71256 is packaged in a 28-pin (300 or 600 mil)
ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600
mil) plastic DIP, and 32-pin LCC providing high board-level
packing densities.
The IDT71256 military RAM is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
ADDRESS
DECODER
A
14
262,144 BIT
MEMORY ARRAY
V
CC
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
CONTROL
CIRCUIT
2946 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-2946/7
7.2
1
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
D28-3
P28-1
P28-2
D28-1
SO28-5
23
22
21
20
19
18
17
16
15
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
TRUTH TABLE
(1)
WE
X
X
H
H
L
CS
H
V
HC
L
L
L
OE
X
X
H
L
X
I/O
High-Z
High-Z
High-Z
D
OUT
D
IN
Function
Standby (I
SB
)
Standby (
ISB1
)
Output Disabled
Read Data
Write Data
2946 tbl 02
NOTE:
1. H = V
IH
, L = V
IL
, X = Don’t Care
2946 drw 02
DIP/SOJ
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Com’l.
Mil.
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output
Current
0 to +70
–55 to +125
–55 to +125
1.0
50
A
7
A
12
A
14
NC
V
CC
WE
INDEX
A
13
T
A
T
BIAS
A
8
A
9
A
11
NC
A
10
–55 to +125
–65 to +135
–65 to +150
1.0
50
°C
°C
°C
W
mA
4
3
2
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
5
6
7
8
9
10
11
12
1
32 31 30
29
28
27
26
25
24
23
22
T
STG
P
T
I
OUT
L32-1
OE
21
13
14 15 16 17 18 19 20
I/O
7
I/O
6
CS
2946 drw 03
NOTE:
2946 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.
PIN DESCRIPTIONS
Name
A
0
–A
14
I/O
0
–
I/O
7
Addresses
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
Power
2946 tbl 01
I/O
1
I/O
2
GND
NC
I/O
3
I/O
4
I/O
5
32-Pin LCC
TOP VIEW
Description
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max. Unit
11
11
pF
pF
CS
WE
OE
GND
V
CC
NOTE:
2946 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
7.2
2
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2946 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max. Unit
5.5
0
6.0
0.8
V
V
V
V
NOTE:
2946 tbl 06
1. V
IL
(min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
(1, 2)
(V
CC
= 5.0V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
71256S/L20
Symbol
I
CC
Parameter
Dynamic Operating Current
CS
≤
V
IL
, Outputs Open
V
CC
= Max., f = f
MAX(2)
Standby Power Supply
Current (TTL Level)
CS
≥
V
IH
, V
CC
= Max.,
Outputs Open, f = f
MAX(2)
Full Standby Power Supply
Current (CMOS Level)
CS
≥
V
HC
, V
CC
= Max., f = 0
Power Com’l.
S
L
S
L
S
L
—
135
—
3
—
0.4
Mil.
—
—
—
—
—
—
71256S/L25
Com’l.
—
115
—
3
—
0.4
Mil.
150
130
20
3
20
1.5
71256S/L30
Com’l.
—
—
—
—
—
—
Mil.
145
125
20
3
20
1.5
71256S/L35
Com’l.
—
105
—
3
—
0.4
Mil.
140
120
20
3
20
1.5
mA
mA
Unit
mA
I
SB
I
SB1
71256S/L45
Symbol
I
CC
Parameter
Dynamic Operating Current
CS
≤
V
IL
, Outputs Open
V
CC
= Max., f = f
MAX(2)
Standby Power Supply
Current (TTL Level)
CS
≥
V
IH
, V
CC
= Max.,
Outputs Open, f = f
MAX(2)
Full Standby Power Supply
Current (CMOS Level)
CS
≥
V
HC
, V
CC
= Max., f = 0
71256S/L55
71256S/L70
Com’l.
—
—
—
—
—
—
71256S/L85
(3)
71256S/L100
(3)
Mil.
135
115
20
3
20
1.5
2946 tbl 07
Power Com’l. Mil. Com’l. Mil.
S
L
S
L
S
L
—
100
—
3
—
0.4
135
115
20
3
20
1.5
—
—
—
—
—
—
135
115
20
3
20
1.5
Mil. Com’l. Mil. Com'l.
135
115
20
3
20
1.5
—
—
—
—
—
—
135
115
20
3
20
1.5
—
—
—
—
—
—
Unit
mA
I
SB
mA
I
SB1
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
, all address inputs cycling at f
MAX
; f = 0 means no address pins are cycling.
3. Also available: 120 and 150 ns military devices.
7.2
3
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2946 tbl 08
5V
480
Ω
DATA
OUT
255
Ω
30pF*
DATA
OUT
255
Ω
5V
480
Ω
5pF*
2946 drw 04
2946 drw 05
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, t
WHZ
)
*Includes scope and jig capacitances
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT71256S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Condition
V
CC
= Max.,
V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH,
V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OL
= 10mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= –4mA, V
CC
= Min.
—
2.4
MIL.
COM’L.
MIL.
COM’L.
Min.
—
—
—
—
Typ.
—
—
—
—
—
—
—
Max.
10
5
10
5
0.4
0.5
—
IDT71256L
Min.
—
—
—
—
—
—
2.4
Typ.
—
—
—
—
—
—
—
Max.
5
2
5
2
0.4
0.5
—
V
2946 tbl 09
Unit
µA
µA
V
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) V
LC
= 0.2V, V
HC
= V
CC
– 0.2V
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR
t
R(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Test Condition
—
MIL.
COM’L.
Min.
2.0
—
—
0
t
RC(2)
2.0v
—
—
—
—
—
3.0V
—
—
—
—
—
2.0V
—
500
120
—
—
Max.
V
CC
@
3.0V
—
800
200
—
—
Unit
V
µA
ns
ns
2946 tbl 10
CS
≥
V
HC
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed, but not tested.
7.2
4
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW V
CC
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
V
DR
≥2V
V
IH
V
DR
V
IH
2946 drw 06
V
CC
t
CDR
CS
4.5V
4.5V
t
R
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
71256L20
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(2)
t
CHZ
(2)
t
OE
t
OLZ
(2)
t
OHZ
(2)
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
20
—
—
5
—
—
2
2
5
—
20
20
—
10
10
—
8
—
25
—
—
5
—
—
2
2
5
—
25
25
—
11
11
—
10
—
30
—
—
5
—
—
2
2
5
—
30
30
—
15
13
—
12
—
35
—
—
5
—
—
2
2
5
—
35
35
—
15
15
—
15
—
45
—
—
5
—
—
0
—
5
—
45
45
—
20
20
—
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
(1)
71256S25
71256L25
Min. Max.
71256S30
(3)
71256L30
(3)
Min.
Max.
71256S35
71256L35
Min.
Max.
71256S45
71256L45
Min. Max. Unit
Max.
Write Cycle
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
WHZ
(2)
t
DH
t
OW
(2)
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Write Enable to Output in High-Z
Data Hold from Write Time
Output Active from End-of-Write
20
15
15
0
15
0
11
—
0
5
—
—
—
—
—
—
—
10
—
—
25
20
20
0
20
0
13
—
—
—
—
—
—
—
11
—
—
30
25
25
0
25
0
14
—
0
5
—
—
—
—
—
—
—
15
—
—
35
30
30
0
30
0
15
—
0
5
—
—
—
—
—
—
—
15
—
—
45
40
40
0
35
0
20
—
0
5
—
—
—
—
—
—
—
20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2946 tbl 11
—
0
5
NOTES:
1. 0° to +70°C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. –55° to +125°C temperature range only.
7.2
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
